Field programmable object array having image processing circuitry
AssigneeNytell Software LLC
InventorsDean Stuart Susnow, Richard D. Reohr, JR.
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Abstract
A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.
Claims20
A device, comprising:
- a direct memory access engine configured to route first search window pixel data from a memory to a video compression processor via a first bus of two multi-bit periphery buses supporting data flow in a first direction and a second bus of the two multi-bit periphery buses supporting data flow in a second direction;
- and
- communication circuitry configured to route second search window pixel data from the memory to the video compression processor via multiple channels of an array of programmable gates at a higher transfer rate relative to the direct memory access engine, wherein the communication circuitry is further configured to transfer at least a portion of the search widow pixel data via the multiple channels during a single clock cycle.
A circuit, comprising:
- a memory communicatively coupled to an array of programmable gates via communication circuitry;
- and
- a video compression processor is configured to:
- collect search window pixel data from the memory via the communication circuitry and at least one of the programmable gates in response to initiation of a first type operation of an application process;
- and
- collect the search window pixel data from the memory via a data transfer engine in response to initiation of a second type of operation of the application process,
- wherein at least a portion of the search window pixel data is configured to be transferred via multiple channels of the communication circuitry during a given clock cycle, and
- wherein the data transfer engine is configured to transfer the search window pixel data at a lower transfer rate than the communication circuitry via two multi-bit periphery buses that bypass the array of programmable gates and respectively facilitate two different data flow directions.
A method, comprising:
- in response to determining that an application process is performing a first type of operation, transferring, by a system comprising a processor, search window pixel data, from a memory of an array of programmable gates to a video compression processor via multiple channels, per clock cycle, of a circuit that connects the memory to the video compression processor via the array of programmable gates;
- and
- in response to determining that the application process is performing a second type of operation, transferring the search window pixel data from the array of programmable gates to the video compression processor via two multi-bit periphery buses associated with a direct memory access engine without routing the search window pixel data via the array of programmable gates, wherein the two multi-bit periphery buses support clockwise data flow around the array of programmable gates and counterclockwise data flow around the array of programmable gates, respectively.
Dependencies are inferred from the claim text.