Matrix-array sensor with temporal coding without arbitration
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsCamille DUPOIRON, Gilles SICARD, Arnaud VERDANT
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AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsCamille DUPOIRON, Gilles SICARD, Arnaud VERDANT
Estimating the term…
A matrix-array sensor comprises a matrix of detection elements arranged in rows and columns and a readout circuit for each column, the elements of one and the same column linked to the corresponding readout circuit via a bus, each element comprising a sensor, a charge integrator configured to accumulate charge generated by the sensor, a comparator configured to generate a trigger signal when a voltage level across the terminals of this comparator reaches a threshold level, and a bus access logic circuit which is configured to receive, as input, the trigger signal and to attempt to transmit, over the bus, an address of the element in the column, wherein the elements of one and the same column have predetermined bus access priority levels, and wherein the bus access logic circuit of each element is configured: to abandon transmission of the address and reset the charge integrator of the detection element if the bus is pre-empted by an element having a higher priority level; to count the number of attempts made before being able to transmit the address; and to communicate the number to the readout circuit along with the address of the element.
A matrix-array sensor comprising a matrix of detection elements that are arranged in rows and in columns and a readout circuit for each column, the detection elements of one and the same column being linked to the corresponding readout circuit via a bus, each detection element comprising a sensor for generating an electric current having an intensity that is representative of a physical quantity to be detected, a charge integrator configured to accumulate charge generated by said sensor, a comparator configured to generate a trigger signal when a voltage level across the terminals of this comparator reaches a threshold level, and a bus access logic circuit configured to receive, as input, said trigger signal and, following reception of said signal, to attempt to transmit, over said bus, an address of said detection element in the column, wherein the detection elements of one and the same column have different bus access priority levels, and wherein said bus access logic circuit of each detection element is configured:
Dependencies are inferred from the claim text.