Homomorphic Processing Unit (HPU) for Accelerating Secure Computations under Homomorphic Encryption
AssigneeThe Governing Council of the University of Toronto
InventorsAlhassan Khedr, Glenn Gulak
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Abstract
Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) homomorphic processor chip is disclosed. The IC homomorphic processor chip includes at least one processor slice. Each processor slice includes local control circuitry, a numeric theoretic transform (NTT) butterfly unit, and on-chip memory. The NTT butterfly unit is responsive to the local control circuitry to operate in multiple modes for performing operations on encrypted data using homomorphic encryption. Each mode is associated with a different configuration of the NTT butterfly unit.
Claims30
An integrated circuit (IC) homomorphic processor chip comprising:
- at least one processor slice, the slice including
- local control circuitry;
- a numeric theoretic transform (NTT) butterfly unit responsive to the local control circuitry to operate in multiple modes for performing operations on encrypted data using homomorphic encryption, each mode associated with a different configuration of the NTT butterfly unit;
- and
- on-chip memory coupled to the control circuitry and the NTT butterfly unit.
A homomorphic encryption system, comprising:
- an integrated circuit (IC) homomorphic processor chip;
- main memory external to the IC homomorphic processor chip;
- a data path for transferring data between the main memory and the IC homomorphic processor chip;
- a control path to control the transfers between the main memory and the IC homomorphic processor chip;
- and
- wherein the IC homomorphic processor chip comprises
- master control circuitry to control the transfers of data between the main memory and the IC homomorphic processor chip via the control path;
- and
- multiple processor slices corresponding to a pipeline depth, each of the multiple processor slices including
- local control circuitry;
- a numeric theoretic transform (NTT) butterfly unit responsive to the local control circuitry to operate in multiple modes for performing operations on encrypted data using homomorphic encryption, each mode associated with a different configuration of the NTT butterfly unit;
- and
- on-chip memory coupled to the local control circuitry and the NTT butterfly unit.
A numeric theoretic transform (NTT) butterfly circuit comprising:
- a high input word path including
- a first adder/subtractor,
- a first multiplier, and
- first selection circuitry coupled to the first adder/subtractor and the first multiplier and including respective bypass paths to selectively bypass the first adder/subtractor and the first multiplier;
- a low input word path including
- a second adder/subtractor,
- a second multiplier, and
- second selection circuitry coupled to the second adder/subtractor and the second multiplier and including respective bypass paths to selectively bypass the second adder/subtractor and the second multiplier;
- wherein the high and low input word paths are cross-coupled, and the first and second selection circuitry is responsive to different mode control signals to reconfigure the low and high input word paths into different logic processing units.
Dependencies are inferred from the claim text.