Analog to digital converter and a method for analog to digital conversion

A method for analog to digital conversion, the method comprises:

• outputting, by a multi-phase clock unit, multiple phase-shifted clock signals that are phase shifted from each other;
• sampling, by a first sampler, during a sampling iteration, a first input analog signal to provide a first voltage signal that represents the first input analog signal;
• generating, by a first pulse width modulation (PWM) modulator that is coupled to the first sampler, a first PWM pulse that represents the first voltage signal;
• sampling, by a second sampler, during the sampling iteration, a second input analog signal to provide a second voltage signal that represents the second input analog signal;
• generating, by a second PWM modulator that is coupled to the second sampler, a second PWM pulse that represents the second voltage signal;
• feeding N counters by the multiple phase-shifted clock signals, wherein the different counters are fed by different phase-shifted clock signals that are evenly phase shifted from each other;
• N being an integer;
• sampling, by a first sampling latch of each pair of N sampling latches, an output of a corresponding counter at (a) a start of the first PWM pulse, and at (b) an end of the first PWM pulse, to provide a first PWM pulse start counter value and a first PWM pulse end counter value;
• sampling, by a second sampling latch of each pair of N sampling latches, an output of a corresponding counter at (a) a start of the second PWM pulse, and at (b) an end of the second PWM pulse, to provide a second PWM pulse start counter value and a second PWM pulse end counter value;
• receiving, by a processing unit, from first sampling latches of the N pairs of sampling latches, N first PWM pulse start counter values and N first PWM pulse end counter value;
• receiving, by the processing unit, from second sampling latches of the N pairs of sampling latches, N second PWM pulse start counter values and N second PWM pulse end counter value;
• selecting, by the processing unit, a counter that is coupled to a selected sampling latch;
• calculating, by the processing unit, an estimated difference between the first input analog signal and the second input analog signal based on at least readings of the selected latch;
• wherein the readings of the selected counter comprise a first PWM pulse start counter value latched by the selected latch, a first PWM pulse end counter value latched by the selected latch, a second PWM pulse start counter value latched by the selected latch, and a second PWM pulse end counter value latched by the selected latch;
• and
• outputting a digital output signal indicative of the estimated difference.

An analog to digital converter comprising:

• a multi-phase clock unit that is configured to output multiple phase-shifted clock signals that are phase shifted from each other;
• a first voltage to time sampling de-multiplexer that comprises a first demultiplexer and first plurality of first time to voltage units;
• wherein the first demultiplexer is configured to receive a sequence of first plurality of first input analog signals, and to distribute the sequence of first plurality of first input analog signals between the first plurality of first voltage to time units, so that each first voltage to time unit receives a different first input analog signal of the sequence of first plurality of first input analog signals;
• wherein each first voltage to time unit comprises a first voltage dependent delay circuit that is configured to output a first pulse that has a duration that is indicative of a value of a first input analog signal fed to the first voltage to time unit;
• a second voltage to time sampling de-multiplexer that comprises a second demultiplexer and first plurality of second time to voltage units;
• wherein the second demultiplexer is configured to receive a sequence of first plurality of first input analog signals, and to distribute the sequence of first plurality of second input analog signals between the first plurality of second voltage to time units, so that each second voltage to time unit receives a different second input analog signal of the sequence of first plurality of second input analog signals;
• wherein each second voltage to time unit comprises a second voltage dependent delay circuit that is configured to output a second pulse that has a duration that is indicative of a value of a second input analog signal fed to the second voltage to time unit;
• a second plurality of counters, wherein different counters are fed by different phase-shifted clock signals, wherein the different phase-shifted clock signals are evenly phase shifted from each other;
• first plurality of being an integer;
• a first plurality of pairs of timing units;
• wherein each pair of timing units is (a) coupled to a different pair of first time to voltage unit and a second time to voltage unit, and (b) is configured to determine a difference in phase-shifted clock signals between an end of the first pulse generated by the first time to voltage unit and an end of the second pulse generated by the second time to voltage unit;
• and
• at least one processing unit that is fed by the first plurality of timing unit and is configured to generate a first plurality of digital output signals indicative of differences between the first plurality of first input analog signals and corresponding second plurality of second input analog signals.