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US 2018/0294816 A1Published application
Scaleable dll clocking system
AssigneeMicrosoft Technology Licensing, LLC
InventorsRichard MCCAULEY, Barry THOMPSON, Stefan WURSTER
Life of this patent
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Abstract
A clocking system disclosed herein includes a delay locked loop (DLL) circuit with a plurality of delay elements, where the DLL circuit is configured to receive a clock input signal and generate a plurality of clock output signals. The clocking system also includes a feed-forward system configured to increase the speed of the clock signal transmission through the delay elements and to enforce symmetric zero crossings of the clock signal at each of the plurality of delay elements.
Claims20
A system, comprising:
- a plurality of feed-forward elements configured to increase speed of a clock signal transmission through a plurality of delay elements,
- wherein successive delay elements generate phase signals that are substantially 180 degree out of phase.
A scalable DLL clocking system, comprising:
- a delay locked loop (DLL) circuit with a plurality of delay elements, the DLL circuit configured to receive a clock input signal and generate a plurality of clock output signals;
- and
- a feed-forward system configured to increase the speed of the clock signal transmission through the delay elements and to enforce symmetric zero crossings of the clock signal at each of the plurality of delay elements.
A system, comprising:
- a delay locked loop (DLL) circuit with a plurality of delay elements, the DLL circuit configured to receive a clock input signal;
- and
- a feed-forward system configured to increase the speed of the plurality of combinations of phase A signals and phase B signals through the delay elements.
Dependencies are inferred from the claim text.