Dynamic biasing circuitry for level-shifter circuitry

A device comprising a single semiconductor die including:

• half-bridge circuitry comprising a high-side power switch and a low-side power switch, wherein the high-side power switch and the low-side power switch are electrically connected by a switch node;
• level-shifter circuitry;
• gate driver circuitry configured to deliver control signals to a control terminal of the high-side power switch based on shifted pulse-width modulated signals received from the level-shifter circuitry;
• and
• biasing circuitry comprising:
• at least four diodes, wherein each diode of the at least four diodes is electrically connected in series;
• a high-side capacitor and a low-side capacitor;
• push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to deliver an intermediate voltage signal to the high-side capacitor and the low-side capacitor, wherein the biasing circuitry is configured to:
• deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal delivered to the high-side capacitor and further based on a high-side voltage signal from the at least four diodes, and
• deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal delivered to the low-side capacitor and further based on a low-side voltage signal from the at least four diodes.