High-frequency semiconductor amplifier circuit

A multi-band semiconductor amplifier circuit, comprising:

• a bias generation circuit connected to a power supply terminal and reference voltage terminal and having a plurality of input control signal terminals at which a plurality of input control signals can be input;
• a first input terminal at which a first high-frequency signal can be input;
• a second input terminal at which a second high-frequency signal can be input;
• a first output terminal at which a high-frequency signal can be output;
• a first high-frequency amplifier circuit connected between the first input terminal and the first output terminal, the first high-frequency amplifier circuit comprising:
• a first transistor having a gate connected to the first input terminal via a first capacitor;
• a second transistor connected between a source of the first transistor and a reference potential terminal;
• and
• a third transistor having a source connected to a drain of the first transistor and a drain connected to the first output terminal via a second capacitor;
• a second high-frequency amplifier circuit connected between the second input terminal and the first output terminal, the second high-frequency amplifier circuit comprising:
• a fourth transistor having a gate connected to the second input terminal via a third capacitor, a source of the fourth transistor being connected to the gate of the fourth transistor via a fourth capacitor;
• a fifth transistor connected between the source of the fourth transistor and the reference potential terminal;
• and
• a sixth transistor having a source connected to a drain of the fourth transistor and a drain connected to the first output terminal via the second capacitor, wherein
• the bias generation circuit is configured to:
• supply a first voltage at a first voltage terminal, the first voltage being between a power supply voltage supplied at the power supply terminal and a reference voltage supplied at the reference voltage terminal, the first voltage terminal being connected to the drain of the third transistor and the drain of the sixth transistor,
• supply control signals to the gates of the second and fifth transistors according to the plurality of input control signals,
• supply first bias voltages to the gates of the first and fourth transistors according to the plurality of input control signals, and
• supply second bias voltages to the gates of third and sixth transistors according to the plurality of input control signals.