Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a finfet device

A method of forming epi semiconductor material on a recessed fin in source/drain regions of a FinFET device, comprising:

• forming a gate structure around a fin and above a layer of insulating material;
• forming a gate spacer adjacent said gate structure and a fin spacer positioned adjacent opposing lateral sidewalls of said fin in said source/drain regions above said layer of insulating material, said fin spacer and said gate spacer comprising a same material, said fin spacer leaving an upper surface of said fin exposed;
• performing at least one etching process to remove at least a first portion of said fin positioned between said fin spacer and a second portion of said fin disposed laterally beneath said gate spacer, said fin having a recessed upper surface that at least partially defines a fin recess positioned between said fin spacer, wherein a portion of said fin recess extends laterally under at least a portion of said gate spacer defined by the removal of said second portion;
• forming a doped epi semiconductor material on said recessed upper surface of said fin and within said fin recess, wherein said doped epi semiconductor material has a first concentration of a first type of dopant;
• removing said fin spacer from adjacent said doped epi semiconductor material while leaving a portion of said gate spacer in position adjacent said gate structure;
• forming a doped region in said doped epi semiconductor material, wherein said doped region has a second concentration of said first type of dopant that is greater than said first concentration;
• and
• forming a conformal epi cladding layer on substantially all surfaces of said doped epi semiconductor material positioned above said layer of insulating material.

A method of forming epi semiconductor material on a recessed fin in source/drain regions of a FinFET device, comprising:

• forming a gate structure around a fin and above a layer of insulating material;
• forming a gate spacer adjacent said gate structure and a fin spacer positioned adjacent opposing lateral sidewalls of said fin in said source/drain regions above said layer of insulating material, said fin spacer and said gate spacer comprising a same material, said fin spacer leaving an upper surface of said fin exposed;
• performing at least one etching process to remove at least a portion of said fin positioned between said fin spacer, said fin having a recessed upper surface that at least partially defines a fin recess positioned between said fin spacer;
• forming an epi semiconductor material on said recessed upper surface of said fin and within said fin recess;
• and
• performing an anisotropic reactive ion etching process to remove said fin spacer from adjacent said epi semiconductor material while leaving a portion of said gate spacer in position adjacent said gate structure.