Tft substrate manufacturing method and tft substrate

A thin film transistor (TFT) substrate, comprising:

• a base substrate, a buffer layer covering the base substrate, an active layer disposed on the buffer layer, a gate insulation layer covering the active layer and the buffer layer, two first through-holes penetrating the gate insulation layer, two bridging metal blocks respectively inside the two first through-holes, a gate disposed on the gate insulation layer, an interlayer dielectric layer covering the gate and the gate insulation layer, two second through-holes penetrating the interlayer dielectric layer, a source and a drain distributed with a gap disposed on the interlayer dielectric layer, and a planarization layer, a common electrode, a passivation layer, and a pixel electrode, stacked from the bottom up, disposed on the source, drain and the interlayer dielectric layer;
• the active layer comprising:
• a channel, two ion heavily doped areas located respectively at two sides of the channel, and two ion lightly doped areas located respectively between the channel and the two ion heavily doped areas;
• the two first through-holes being located respectively above the two ion heavily doped areas, the two bridging metal blocks contacting respectively the two ion heavily doped areas, and the gate being located on the gate insulation layer above the channel;
• the two second through-holes connected respective the two first through-holes, and the source and the drain contacting the two bridging metal blocks through the two second through-holes respectively.

A thin film transistor (TFT) substrate manufacturing method, comprising the steps of:

• Step 1:
• providing a base substrate, and forming, in subsequent order of, a buffer layer and an active layer on the base substrate;
• performing ion doping at two ends of the active layer to form two ion heavily doped areas;
• forming a gate insulation layer on the active layer and the buffer layer;
• Step 2:
• forming a photo-resist layer on the gate insulation layer, performing etching and exposure with a half tone mask on the photo-resist layer to form a first groove and two first vias on the photo-resist layer;
• the first groove being located above a channel area to be formed between the two ion heavily doped areas, and the two first vias being located respectively above the two ion heavily doped areas;
• Step 3:
• using the remaining photo-resist layer as shielding to perform etching on the gate insulation layer to form two first through-holes at locations corresponding respectively to below the two first vias;
• Step 4:
• performing an overall thinning process on the photo-resist layer to transform the first groove into a second via;
• using the remaining photo-resist layer as shielding to perform ion doping on the active layer to form a channel at locations below the second via;
• Step 5:
• peeling the remaining photo-resist layer, depositing a first metal layer on the gate insulation layer, performing patternizing on the first metal layer to obtain a gate corresponding to a location above the channel, and two bridging metal blocks located respectively inside the two first through-holes;
• Step 6:
• using the gate as shielding to perform ion doping on the active layer to obtain two ion lightly doped areas located respectively between the channel and the two ion heavily doped areas;
• Step 7:
• forming an interlayer dielectric layer on the gate insulation layer, performing etching on the interlayer dielectric layer to form two second through-holes respectively above the two bridging metal blocks;
• Step 8:
• depositing a second metal layer on the interlayer dielectric layer, performing patternizing on the second metal layer to obtain a source and a drain distributed with a gap on the interlayer dielectric layer, the source and the drain contacting the two bridging metal blocks through the two through-holes;
• Step 9:
• forming on the interlayer dielectric layer, in subsequent order of, a planarization layer, a common voltage, a passivation layer, and a pixel electrode, stacked from bottom up;
• wherein the etching on the gate insulation layer in Step 3 and the etching on the interlayer dielectric layer in Step 7 being both dry etching;
• wherein in Step 4, the overall thinning processing on the photo-resist layer being a photo-resist ashing method.