Approach to the manufacturing of monolithic 3-dimensional high-rise integrated-circuits with vertically-stacked double-sided fully-depleted silicon-on-insulator transistors
OwnerAhmad Tarakji, Nirmal Chaudharyinventors
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Abstract
Method to fabricate high-rise three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all the other known methods and prior arts to fabricate or manufacture 3D-ICs in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAs in monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.
Claims6
The use of Dual-Sided Contacts to Drain and Source to shorten Inline interconnects between any two devices (e.g. transistors) that are vertically stacked on top of one another in Three-Dimensional Integrated-Circuits (3D-ICs);
- Dual-Sided Contacts are Ohmic Contacts that are applied or distributed on two opposing sides (surfaces) of a semiconductor;
- this shortening of the Inline interconnects is accomplished through enabling the top Contacts of the bottom devices to interconnect to the bottom Contacts of higher vertically stacked devices;
- this claim is specific to the mid-section process;
- it therefore extends to all and any devices and transistors to which Dual-Sided Contacts are or can be processed;
The use of Dual-Sided-Fully-Depleted-Silicon-On-Insulator MOS (DS-FD-SOI-MOS) transistors as building-blocks to monolithic Three-Dimensional Integrated-Circuits (3D-ICs) for high on-state performance and low off-state leakage;
- the high performance and low off-state leakage are largely attributed from the capability to modulate this device Threshold-Voltage (VT) through independently controlling and tuning one of its two Gates to accommodate best off-state power and performance;
- higher performance is also largely attributed to the much shorter Inline interconnects between the 3D-integrated device, included are the Inline interconnects between devices (transistors) that are vertically stacked on top of one another;
- these DS-FD-SOI-MOS transistors can be used to form all Logic and Memory modules in 3D-ICs (these are any forms of Memories:
- SRAMs, DRAMs, MRAMs, etc . . . );
- DS-FD-SOI MOS are transistors that are fully immersed in Inline dielectric and have exact same Contacts to their Drain and Source, and same or similar insulating Gates to their front-surface and back-surface, (back-surface is their reverse-side surface relative to their front-surface);
- they are solely made of electrically active Silicon without the thick bulky substrates that induce unwanted parasitic effects, contribute to unnecessary increase in the heights of 3D-ICs, and cause lower electric conductivities from interconnecting the vertically stacked devices through them with Through-Silicon-VIAs (TSVs);
- the devices channels can be any forms, strained or unstrained, recessed (having raised Source and Drain) or un-recessed, and the semiconductor films can be either composed of plain Silicon or with its compounds (e.g. SiGe);
The use of DS-FD-SOI MOS transistors as special-purpose switches for active 3D-routing that can reconfigure Hardware architectures in 3D;
The technique to bond two vertically stacked Silicon layers together through their Inline dielectrics and then pattern and form the inter-wires that connect these two layers together;
- this is being accomplished with a deep trench etch through the Isolation-trenches down to the higher interconnect-Layer of the bottom Silicon layer;
- SLAM is then deposited to fill this deep etched trench;
- this is followed with patterning and etching for interconnecting the higher interconnect-Layer of the bottom Silicon layer to the lower interconnect-Layer of the top Silicon layer;
- finally inter-wires are formed (e.g. with Sputtering & Electroplating) to physically interconnect (or inter-wire) the two Silicon layers together;
- while forming these inter-wires selective etch of the SLAM is done first to expose the ESL in the higher interconnect-Layer of the bottom Silicon layer;
- this is followed with another selective etch of the Inline dielectric to expose the ESL in the lower interconnect-Layer of the upper Silicon layer;
- the etch chemistry is then switched one last time to etch the ESLs in both interconnect-Layers;
The technique to directly thermally-bond the different Silicon layers together through both their Inline dielectrics and their interconnect-Layers;
- for this, the Inline dielectrics of the Silicon layers to be bonded are first thoroughly polished to expose their Inline interconnect-Layers;
- this is then followed with thermo-compression bonding. Interconnect-layers made of Copper Metals are good choice for this bonding technique as they can bond at high temperatures (˜1000 DegC), and at temperatures as low 250-300 DegC.
The technique to align for lithography the front surface of a thinned layer of Silicon to its back surface through forming deep Isolation-trenches on one surface of the seed-Wafer, fully processing that one side, and bonding it through its Inline dielectric to the dielectric surface of a Handle-Wafer. The Back Silicon of this seed-wafer is then excessively thinned through etch and/or polish to expose these Isolation-trenches from their opposite side (surface). These exposed isolation-trenches can then be selectively etched and recessed, and can be used for precision front-to-back alignment.
Dependencies are inferred from the claim text.