Integrated circuit including interconnection for mitigating electromigration and method of fabricating the same

An integrated circuit comprising:

• a first conductive pattern in a first conductive layer;
• a second conductive pattern in a second conductive layer over the first conductive layer;
• and
• a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern to pass through and to allow a second current flowing from the second conductive pattern to the first conductive pattern to pass through,
• wherein the via is on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

A method of fabricating an integrated circuit including a plurality of standard cells, the method comprising:

• performing routing by creating, with reference to a cell library, a plurality of interconnections connecting input pins and output pins of the plurality of standard cells;
• and
• generating layout data defining the plurality of interconnections,
• wherein the performing the routing comprises placing a via comprised in the plurality of interconnections on a third region between a first region of a conductive pattern and a second region of the conductive pattern,
• wherein the conductive pattern corresponds to an output pin of at least one of the plurality of standard cells,
• wherein the first region comprises at least one first point through which a current is supplied from outside the conductive pattern, and
• wherein the second region comprises at least one second point through which a current is drawn to outside the conductive pattern.