Three dimensional semiconductor memory devices

A three-dimensional semiconductor memory device comprising:

• a substrate including a peripheral circuit region and a cell array region;
• an electrode structure including word lines vertically stacked on the substrate of the cell array region, the word lines including a lower word line positioned from a top surface of the substrate at a first distance and an upper word line positioned from the top surface of the substrate at a second distance greater than the first distance;
• a first pass transistor disposed on the substrate of the peripheral circuit region and connecting a row decoder to the lower word line;
• and
• a second pass transistor disposed on the substrate of the peripheral circuit region and connecting the row decoder to the upper word line, wherein
• the first pass transistor comprises m first sub-transistors connected to the lower word line, and the second pass transistor comprises n second sub-transistors connected to the upper word line, wherein n and m are natural numbers.

A manufacturing method for a three-dimensional semiconductor memory device, the manufacturing method comprising:

• forming a memory cell string vertically extending from a top surface of a substrate and including first and second cell transistors;
• forming first and second address lines connected to gate electrodes of the first and second cell transistors, respectively;
• forming a first pass transistor device, having a first effective gate width, connecting the first address line to a row decoder;
• and
• forming a second pass transistor device, having a second effective gate width, connecting the second address line to the row decoder, the second effective gate width being different than the first effective gate width so as to reduce a time difference in transmitting a driving signal from the row decoder to each of the first and second address lines.