Method for fabricating microelectronic package with surface mounted passive element
AssigneeMediatek Inc.
InventorHsing-Chih Liu
Life of this patent
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Abstract
A method for fabricating a microelectronic package is disclosed. A packaged substrate having a chip surrounded by a molding compound is prepared. An RDL structure is formed on the chip. Bump pads and SMD pads are disposed in a topmost level of metal interconnect of the RDL structure. A passivation layer covers the RDL structure. The passivation layer is subjected to a lithographic process to form bump pad openings and an SMD opening in the passivation layer. The bump pads are exposed, respectively, through the bump pad openings. The SMD pads are exposed through the SMD opening. Bumps are formed on the bump pads through the bump pad openings, respectively. A passive element is mounted on the SMD pads.
Claims21
A method for fabricating a microelectronic package, comprising:
- providing a packaged substrate having thereon at least one chip surrounded by a molding compound;
- forming a re-distribution layer (RDL) structure on the chip, the RDL structure comprising n levels of metal interconnect, wherein n is an integer that is greater than or equal to 2, wherein bump pads and surface mount device (SMD) pads are disposed in a topmost level of the n levels of metal interconnect of the RDL structure;
- forming a passivation layer covering the RDL structure;
- subjecting the passivation layer to a lithographic process to form bump pad openings and an SMD opening in the passivation layer, wherein the bump pads are exposed, respectively, through the bump pad openings, and the SMD pads are exposed through the SMD opening;
- forming bumps on the bump pads through the bump pad openings, respectively;
- and
- mounting a passive element on the SMD pads.
A method for fabricating a microelectronic package, comprising:
- providing a packaged substrate having thereon at least one chip surrounded by a molding compound;
- forming a re-distribution layer (RDL) structure on the chip, the RDL structure comprising n levels of metal interconnect, wherein n is an integer that is greater than or equal to 2, wherein bump pad and surface mount device (SMD) pads are disposed in a topmost level of the n levels of metal interconnect of the RDL structure;
- forming a passivation layer covering the RDL structure;
- subjecting the passivation layer to a lithographic process to form bump pad openings in the passivation layer, wherein the bump pads are exposed, respectively, through the bump pad openings;
- forming under-bump metallization (UBM) pads and SMD pads on the passivation layer;
- forming solder balls or bumps on the UBM pads, respectively;
- and
- mounting a passive element on the SMD pads.
A method for fabricating a microelectronic package, comprising:
- providing a packaged substrate having thereon at least one chip surrounded by a molding compound;
- forming a re-distribution layer (RDL) structure on the chip, the RDL structure comprising n levels of metal interconnect in a dielectric layer, wherein n is an integer that is greater than or equal to 2, wherein bump pads are disposed in a topmost level of the n levels of metal interconnect of the RDL structure, and surface mount device (SMD) pads are disposed in a lowest level of the n levels of metal interconnect of the RDL structure;
- forming a passivation layer covering the RDL structure;
- subjecting the passivation layer to a lithographic process to form bump pad openings in the passivation layer and an SMD opening in the passivation layer and the dielectric layer, wherein the bump pads are exposed, respectively, through the bump pad openings, and the SMD pads are exposed through the SMD opening;
- forming bumps on the bump pads through the bump pad openings, respectively;
- and
- mounting a passive element on the SMD pads within the SMD opening.
Dependencies are inferred from the claim text.