Stacked package assembly with voltage reference plane
AssigneeIntel Corporation
InventorsBok Eng CHEAH, Jackson Chung Peng KONG, Ping Ping OOI, Kooi Chi OOI, Shanggar PERIAMAN
Life of this patent
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Abstract
Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
Claims22
-21. (canceled)
A stacked package assembly comprising:
- a first die package and a second die package stacked one upon the other with plural interconnections between them;
- and
- a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
A method of fabricating a stacked package assembly, the method comprising:
- forming a first die package having an embedded first integrated circuit die, the forming the first die package including forming on the first die package a voltage reference plane substantially encompassing the first die package;
- forming a second die package having an embedded second integrated circuit die;
- and
- stacking the first die package and the second die package together with the embedded voltage reference plane in proximity to the second die package, the stacking the first die package and the second die package together including forming plural electrical interconnections between the first die package and the second die package.
A computing device comprising:
- a circuit board;
- and
- a stacked package assembly coupled with the circuit board, the package assembly comprising:
- first die package and a second die package with a first integrated circuit die and a second integrated circuit die, respectively, the first die package and the second die package being stacked one upon the other with plural interconnections between them;
- and
- a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
Dependencies are inferred from the claim text.