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US 2018/0294221 A1Published application
Semiconductor device, electronic circuit having the same, and semiconductor device forming method
AssigneeRenesas Electronics Corporation
InventorShinichi Uchida
Life of this patent
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Abstract
A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.
Claims20
A semiconductor device comprising:
- a plurality of first wires formed in a first layer and configured to indicate a fixed potential;
- and
- an inductor formed in a second layer stacked on the first layer,
- wherein a wiring width of the first wiring located within a range of a formation region of the inductor in a plan view among the plurality of first wires is formed narrower than a wiring width of the first wiring located outside the range of the formation region of the inductor.
1 more element
A semiconductor device comprising:
- a plurality of first wires formed in a first layer;
- a plurality of second wires formed to intersect the plurality of first wires in a second layer stacked on the first layer;
- a plurality of first vias formed at intersections of the plurality of first wires and the plurality of second wires;
- and
- an inductor formed in a third layer stacked on the first layer and the second layer,
- wherein the plurality of first vias are disposed such that a length of a loop having a minimum length among a plurality of current path loops formed by the plurality of first wires, the plurality of second wires and the plurality of first vias in a plan view is longer than a predetermined length.
3 more elements
A method for forming a semiconductor device comprising:
- forming in a first layer a plurality of first wires configured to indicate a fixed potential;
- and
- forming an inductor in a second layer stacked on the first layer,
- wherein, in the forming the plurality of first wires, a wiring width of the first wire located within a range of a formation region of the inductor in a plan view among the plurality of first wires is narrowed compared to a wiring width of the first wire located outside the range of the formation region of the inductor.
1 more element
Dependencies are inferred from the claim text.