Semiconductor package including a rewiring layer with an embedded chip

A semiconductor package, comprising:

• a substrate;
• a first rewiring layer disposed on an upper surface of the substrate, and having a concave portion;
• a bridge layer formed in the concave portion of the first rewiring layer, the bridge layer including a second semiconductor chip, the second semiconductor chip including a plurality of second wiring patterns;
• a first semiconductor chip and a third semiconductor chip disposed on the first rewiring layer and the bridge layer and being spaced apart from each other in a horizontal direction, and each of the first semiconductor chip and the third semiconductor chip being overlapped with at least a portion of the first rewiring layer and at least a portion of the bridge layer respectively;
• a plurality of second connection terminals formed on the first rewiring layer and electrically connecting the first rewiring layer to the first semiconductor chip and the third semiconductor chip, a minimum pitch between the second connection terminals being a first pitch;
• and
• a plurality of third connection terminals formed on the second semiconductor chip and electrically connecting the first semiconductor chip and the third semiconductor chip to the second semiconductor chip respectively, a minimum pitch between the third connection terminals being a second pitch, and the second pitch being smaller than the first pitch,
• wherein the second wiring pattern electrically connect the first semiconductor chip and the third semiconductor chip, and the concave portion is formed through a photolithography process while forming the first rewiring layer.