Array substrate motherboard, array substrate and method of manufacturing the same, and display device

An array substrate, comprising a fan-out region, a testing line region and a display region, the fan-out region and the testing line region being arranged at two opposite sides of the display region respectively, and a sealant arrangement region being arranged between the fan-out region and the display region,

• wherein the array substrate further comprises a plurality of testing buses arranged at the testing line region at different layers, and each testing bus corresponds to a group of first testing lines;
• each group of first testing lines is formed integrally with the testing bus corresponding to the group of first testing lines;
• the fan-out region comprises a connection region and a binding region arranged between the connection region and the sealant arrangement region;
• a plurality of groups of second testing lines is arranged at the fan-out region at different layers;
• one group of second testing lines extends across the connection region to the binding region;
• connection lines and connection members are arranged at the connection region at positions corresponding to remaining groups of second testing lines;
• an end of each connection member is electrically connected to a corresponding group of second testing lines through a first via-hole, and an opposite end of the connection member is electrically connected to a corresponding connection line through a second via-hole;
• and
• each of the connection lines extends to the binding region.

A method of manufacturing an array substrate, comprising steps of:

• forming an array substrate motherboard;
• and
• cutting the array substrate motherboard into a plurality of cutting regions, so as to acquire a plurality of array substrates,
• wherein the step of forming the array substrate motherboard comprises:
• providing a base substrate that is divided into a plurality of array regions and a plurality of testing line regions arranged in one-to-one correspondence with the plurality of array regions, each array region being divided into a fan-out region, a display region and a sealant arrangement region arranged between the fan-out region and the display region, the fan-out region in each array region comprising a connection region arranged adjacent to the testing line region and a binding region arranged adjacent to the sealant arrangement region;
• forming a plurality of groups of testing patterns at different layers that are spaced and insulated from each other, each group of testing patterns comprising a testing bus and a group of testing lines formed integrally with the testing bus, one group of testing lines in one group of testing patterns extending across the connection region to the binding region, and the testing lines in remaining groups of testing patterns not extending to the binding region;
• forming a pattern comprising a plurality of connection lines arranged at the connection region and arranged in one-to-one correspondence with the testing lines not extending to the binding region;
• forming an insulation layer covering the pattern comprising the plurality of connection lines;
• forming a plurality of groups of first via-hole and second via-hole penetrating through the insulation layer, each connection line corresponding to one group of first via-hole and second via-hole, the first via-hole being arranged above the corresponding group of testing lines, and the second via-hole being arranged above the corresponding connection line;
• and
• forming a pattern comprising a plurality of connection members arranged in one-to-one correspondence with the plurality of connection lines, and
• each cutting region comprises one of the array regions and one of the testing line regions, and the testing line region and the fan-out region of the array region are arranged at two sides of the display region of the array region respectively.