US 2018/0294182 A1Published application

A method of manufacturing semiconductor-on-insulator

AssigneeSunEdison Semiconductor Limited (UEN201334164H)

InventorsGang Wang, Shawn George Thomas

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Abstract

The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a Ge(Si)-on-insulator structure or a Ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer is completed with a silicon passivation layer. A cleave plane is formed within the multilayer, and the multilayer structure is bonded to a handle substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleave plane to thereby prepare a semiconductor-on-insulator structure comprising a semiconductor handle substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating pairs of layers, comprising a layer of silicon and a layer of germanium option ally with silicon.

Claims33

Dependent claims

A method of preparing a multilayer structure, the method comprising:

(a) depositing a first layer comprising germanium on a front surface of a silicon substrate, wherein the silicon substrate comprises two major, generally parallel surfaces, one of which is the front surface of the silicon substrate and the other of which is a back surface of the silicon substrate, a circumferential edge joining the front and back surfaces of the silicon substrate, a central plane between and parallel to the front surface and the back surface of the silicon substrate, a central axis perpendicular to the central plane, and a bulk region between the front and back surfaces of the silicon substrate, and further wherein the first layer comprising germanium has a thickness between about 0.5 micrometer and about 100 micrometers, as measured along the central axis;
(b) depositing a second layer comprising silicon on the first layer comprising germanium, wherein the second layer comprising silicon has a thickness between about 0.5 nanometer and about 5 nanometers, as measured along the central axis;
and
(c) depositing a third layer comprising germanium and optionally silicon on the second layer comprising silicon, wherein the third layer comprising silicon and germanium has a formula SixGe1-x, wherein x is between about 0 and about 0.8, molar ratio and further wherein the third layer comprising silicon and germanium has a thickness of at least about 1 nanometer.

1 more element

A method of preparing a semiconductor-on-insulator structure, the method comprising:

forming a cleave plane in a multilayer structure, the multilayer structure comprising (i) a silicon substrate comprising two major, generally parallel surfaces, one of which is a front surface of the silicon substrate and the other of which is a back surface of the silicon substrate, a circumferential edge joining the front and back surfaces of the silicon substrate, a central plane between and parallel to the front surface and the back surface of the silicon substrate, a central axis perpendicular to the central plane, and a bulk region between the front and back surfaces of the silicon substrate, (ii) a germanium layer in interfacial contact with the front surface of the silicon substrate, (iii) at least one pair of layers in interfacial contact with the germanium layer, each pair of layers comprising a silicon layer and a layer comprising germanium and optionally silicon having a formula SixGe1-x, wherein x is between about 0 and about 0.8, molar ratio, and (iv) a silicon passivation layer in contact with the at least one pair of layers, wherein the cleave plane is formed within the at least one pair of layers comprising the silicon layer and the silicon germanium layer;
and
bonding the multilayer structure to a dielectric layer interfacial contact with a front surface of a semiconductor handle substrate, the semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is the front surface of the semiconductor handle wafer and the other of which is a back surface of the semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the semiconductor handle substrate, and a bulk region between the front and back surfaces of the semiconductor handle substrate.

Dependencies are inferred from the claim text.

Facts

Application: 15/574,054Filed 23 May 2016
Priority: 1 Jun 2015
Published: 11 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10P 90/1916
Using bonding: with separation or delamination along an ion implanted layer, e.g. Smart-cut
H10P 14/24
Of semiconductor materials: using chemical vapour deposition [CVD]
H10P 14/2905
Being Group IVA materials: silicon, silicon germanium or germanium
H10P 14/3211
Being Group IVA semiconducting materials: silicon, silicon germanium or germanium