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US 2018/0294043 A1Published application
Semiconductor integrated circuit device including test pads
AssigneeSK hynix Inc.
InventorKwi Dong KIM
Life of this patent
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Abstract
A semiconductor integrated circuit device may include a plurality of semiconductor chips, a scribe lane, connecting wiring, and a selection circuit. Each of the semiconductor chips may include a peripheral circuit. The scribe lane may be positioned between the semiconductor chips. A test pad may be arranged in the scribe lane. The connecting wiring may be connected between the test pad and the peripheral circuit. The selection circuit may be configured to selectively connect or disconnect the connecting wiring.
Claims18
A semiconductor memory device comprising:
- a plurality of semiconductor chips including a peripheral circuit;
- a scribe lane positioned between the semiconductor chips, a test pad arranged in the scribe lane;
- a connecting wiring connected between the test pad and the peripheral circuit;
- and
- a selection circuit arranged on the connecting wiring to connect or separate the connecting wiring.
2 more elements
A semiconductor memory device comprising:
- a plurality of semiconductor chip regions including a memory bank region and a peripheral circuit region;
- a scribe lane positioned at an edge of each of the semiconductor chips;
- a peripheral circuit region arranged in the peripheral circuit;
- at least one test pad arranged in the scribe lane;
- and
- a selection circuit configured to selectively connect the test pad with the peripheral circuit.
3 more elements
Dependencies are inferred from the claim text.