Shift register unit, driving method thereof, gate driver circuit and display device

A method for driving a shift register unit, comprising steps of:

• at an input stage, enabling, by a second pull-down node control unit, a pull-down node to be at a first level under the control of a pull-up node, and enabling, by a first pull-up node control unit, the pull-up node to be at a second level;
• at an output stage, enabling, by the first pull-up node control unit, the pull-up node to be maintained at the second level, and enabling, by the second pull-down node control unit, the pull-down node to be at the first level under the control of the pull-up node;
• at a pull-down stage, enabling the pull-up node to be maintained at the second level, and enabling, by the second pull-down node control unit, the pull-down node to be at the first level under the control of the pull-up node;
• and
• at a pull-down maintenance stage, enabling, by a second pull-up node control unit, the pull-up node to be at the first level under the control of a first clock signal, and enabling, by a first pull-down node control unit, the pull-down node to be at the second level under the control of the first clock signal.

A gate driver circuit, comprising multiple levels of shift register units, wherein

• a second clock signal input end of an (8n-7)th-level shift register unit is configured to receive a first left-side clock signal or a first right-side clock signal;
• a second clock signal input end of an (8n-5)th-level shift register unit is configured to receive a second left-side clock signal or a second right-side clock signal;
• a first clock signal input end of the (8n-7)th-level shift register unit is configured to a third left-side clock signal or a third right-side clock signal;
• a first clock signal input end of the (8n-5)th shift register unit is configured to receive a fourth left-side clock signal or a fourth right-side clock signal;
• a second clock signal input end of an (8n-6)th-level shift register unit is configured to receive the first right-side clock signal or the first left-side clock signal;
• a second clock signal input end of an (8n-4)th-level shift register unit is configured to receive the second right-side clock signal or the second left-side clock signal;
• a first clock signal input end of the (8n-6)th-level shift register unit is configured to the third right-side clock signal or the third left-side clock signal;
• a first clock signal input end of the (8n-4)th-level shift register unit is configured to receive the fourth right-side clock signal or the fourth left-side clock signal;
• a second clock signal input end of an (8n-3)th-level shift register unit is configured to receive the third left-side clock signal or the third right-side clock signal;
• a second clock signal input end of an (8n-1)th-level shift register unit is configured to receive the fourth left-side clock signal or the fourth right-side clock signal;
• a first clock signal input end of the (8n-3)th-level shift register unit is configured to receive the first left-side clock signal or the first right-side clock signal;
• a first clock signal input end of the (8n-1)th-level shift register unit is configured to receive the second left-side clock signal or the second right-side clock signal;
• a second clock signal input end of an (8n-2)th-level shift register unit is configured to receive the third right-side clock signal or the third left-side clock signal;
• a second clock signal input end of an (8n)th-level shift register unit is configured to receive the fourth right-side clock signal or the fourth left-side clock signal;
• a first clock signal input end of the (8n-2)th-level shift register unit is configured to receive the first right-side clock signal or the first left-side clock signal;
• a first clock signal input end of the (8n)th-level shift register unit is configured to receive the second right-side clock signal or the second left-side clock signal;
• n is a positive integer;
• the second left-side clock signal is delayed by one time unit as compared with the first left-side clock signal, the third left-side clock signal is delayed by one time unit as compared with the second left-side clock signal, and the fourth left-side clock signal is delayed by one time unit as compared with the third left-side clock signal;
• the second right-side clock signal is delayed by one time unit as compared with the first right-side clock signal, the third right-side clock signal is delayed by one time unit as compared with the second right-side clock signal, and the fourth right-side clock signal is delayed by one time unit as compared with the third right-side clock signal;
• the first right-side clock signal is delayed by 0.5 time unit as compared with the first left-side clock signal;
• each clock signal has a duty ratio of 0.25, and each clock signal is maintained at the first level for three time units and at the second level for one time unit;
• apart from a first-level shift register unit on the left, a first carry signal input end of a current-level shift register unit on the left is connected to a carry signal output end of an adjacent previous-level shift register unit on the left;
• apart from a first-level shift register unit on the right, a first carry signal input end of a current-level shift register unit on the right is connected to a carry signal output end of an adjacent previous-level shift register unit on the right;
• apart from a last-level shift register unit on the left, a second carry signal input end of a current-level shift register unit on the left is connected to a carry signal output end of an adjacent next-level shift register unit on the left;
• and
• apart from a last-level shift register unit on the right, a second carry signal input end of a current-level shift register unit on the right is connected to a carry signal output end of an adjacent next-level shift register unit on the right.