Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorsDae Hwan YUN, Myeong Won LEE
Life of this patent
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Abstract
Provided herein may be a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation; and a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
Claims20
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory blocks;
- a peripheral circuit configured to apply an erase voltage to a source line and a plurality of select lines of a selected memory block among the plurality of memory blocks during an erase operation;
- and
- a control logic configured to control the peripheral circuit to form a trap in an area below at least one of a plurality of source select transistors included in the selected memory block, before the erase voltage is applied to the selected memory block.
A semiconductor memory device comprising:
- a memory string comprising a source select transistor, a plurality of memory cells, a drain select transistor coupled in series between a source line and a bit line;
- a page buffer coupled to the bit line;
- a voltage generation circuit configured to apply first and second source line control voltages, a pre-erase voltage, and an erase voltage to the source line;
- and
- an address decoder configured to apply first and second setting voltages generated by the voltage generation circuit to the source select transistor,
- wherein, before the pre-erase voltage and the erase voltage are applied to the source line, the first source line control voltage is applied to the source line, and the first setting voltage is applied to the source select transistor.
A method of operating a semiconductor memory device, comprising:
- forming an interface trap in a channel area below a source select transistor by applying a first source line control voltage to a source line of a selected memory block among a plurality of memory blocks and by applying a first setting voltage to at least one first source select transistor disposed at an outermost position among a plurality of source select transistors of the selected memory block;
- removing holes piled up in the channel area by applying a second source line control voltage to the source line and by applying a second setting voltage to the first source select transistor and a second source select transistor adjacent to the first source select transistor, or the first source select transistor and a memory cell adjacent to the first source select transistor;
- and
- erasing the selected memory block by applying an erase voltage to the source line and by controlling word lines of the selected memory block from a floating state to a ground voltage state.
Dependencies are inferred from the claim text.