US 2018/0294033 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

Claims9

Dependent claims

A method of programing a nonvolatile memory cell formed in a main surface of an SOI layer, the nonvolatile memory cell comprising a gate electrode, a source region, a drain region and a charge storage layer between the gate electrode and the SOI layer, the method comprising steps of:

applying a set of programing voltages to the gate electrode and the source and drain regions as a programing step;
and
applying a set of recombining voltages to the gate electrode and the source and drain regions as a recombining step,
wherein, in the programing step, electron carriers are injected to the charge storage layer, and
wherein, in the recombining step, recombining electron carriers are injected to the SOI layer from the source and drain regions and recombine with hole carriers in the SOI layer.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims9