Memory as a programmable logic device
AssigneeMicron Technology, Inc.
InventorsLuca De Santis, Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
Memories including a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, as well as methods of operating similar memories.
Claims20
A memory, comprising:
- a data line;
- a plurality of strings of series-connected memory cells selectively connected to the data line;
- a plurality of first access lines, wherein each first access line of the plurality of first access lines is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- and
- a plurality of second access lines, wherein each second access line of the plurality of second access lines is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.
A method of operating a memory, comprising:
- applying a plurality of first control signals concurrently to control gates of a first string of series-connected memory cells of the memory and to control gates of a second string of series-connected memory cells of the memory, wherein the plurality of first control signals comprises a plurality of pairs of complementary control signals, each pair of complementary control signals of the plurality of pairs of complementary control signals applied to a respective pair of control gates of the first string of series-connected memory cells and to a respective pair of control gates of the second string of series-connected memory cells;
- applying a second control signal to a control gate of a particular memory cell of the first string of series-connected memory cells while applying the plurality of first control signals and without applying the second control signal to a control gate of any memory cell of the second string of series-connected memory cells;
- and
- applying a third control signal to the control gate of a particular memory cell of the second string of series-connected memory cells while applying the plurality of first control signals and while applying the second control signal, and without applying the third control signal to the control gate of any memory cell of the first string of series-connected memory cells.
A method of operating a memory, comprising:
- sensing a state of a first string of series-connected memory cells of the memory;
- storing a result of the sensing of the state of the first string of series-connected memory cells in a page buffer of the memory;
- reading the result of the sensing of the state of the first string of series-connected memory cells from the page buffer into a shift register of the memory;
- selectively activating a particular memory cell of a second string of series-connected memory cells of the memory responsive to the result of the sensing of the state of the first string of series-connected memory cells in the shift register;
- and
- applying a plurality of control signals to control gates of the second string of series-connected memory cells of the memory while selectively activating the particular memory cell of the second string of series-connected memory cells responsive to the result of the sensing of the state of the first string of series-connected memory cells in the shift register, wherein the plurality of control signals comprises a plurality of pairs of complementary control signals, each pair of complementary control signals of the plurality of pairs of complementary control signals applied to a respective pair of control gates of the second string of series-connected memory cells.
Dependencies are inferred from the claim text.