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US 2018/0294030 A1Published application
System and Method for Adjusting EEPROM Write Cycle Duration According to Supply Voltage Variation
AssigneeSTMicroelectronics (Rousset) SAS
InventorsFrancois Tailliet, Marc Battista
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Abstract
A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.
Claims20
A device, comprising:
- a supply voltage node configured to provide a supply voltage;
- a memory cell that is an electrically programmable and erasable read-only memory circuit;
- and
- a write cycle controller configured to:
- provide, to the memory cell, a first write cycle with a first pulse having a first pulse duration, the first pulse comprising a first voltage ramp having a first ramp duration and further comprising a first plateau that is immediately after the first voltage ramp and that has a first plateau duration that is about the same as the first ramp duration;
- and
- provide, to the memory cell, a second write cycle with a second pulse by increasing a second pulse duration of the second pulse in response to a decrease in the supply voltage, the second pulse comprising a second voltage ramp having a second ramp duration longer than the first ramp duration and further comprising a second plateau that is immediately after the second voltage ramp and that has a second plateau duration that is longer than the first plateau duration and that is about the same as the second ramp duration.
4 more elements
A device, comprising:
- a supply voltage node configured to provide a supply voltage;
- a memory cell that is an electrically programmable and erasable read-only memory circuit;
- and
- a write cycle controller configured to:
- provide, to the memory cell, in response to the supply voltage falling below a first step value, a first write cycle with a first pulse having a first pulse duration that is longer that a previous pulse duration of a previous pulse having a previous ramp of a previous ramp duration and further having a previous plateau immediately after the previous ramp and of a previous plateau duration that is about the same as the previous ramp duration, wherein the first pulse comprises a first voltage ramp having a first ramp duration longer than the previous ramp duration, wherein the first pulse further comprises a first plateau that is immediately after the first voltage ramp and that has a first plateau duration that is longer than a previous plateau duration of the previous pulse and that is about the same as the first ramp duration.
2 more elements
A device, comprising:
- a supply voltage node configured to provide a supply voltage;
- a memory cell that is an electrically programmable and erasable read-only memory circuit;
- and
- a write cycle controller, comprising:
- a comparator connected to the supply voltage node and configured to compare the supply voltage to a first step value;
- a pulse generator;
- a driver connected to the pulse generator, the driver configured to cause, in response to the comparator indicating that the supply voltage falls below the first step value, the pulse generator to provide a first write cycle with a first pulse having a first pulse duration that is longer that a previous pulse duration of a previous pulse having a previous ramp of a previous ramp duration and further having a previous plateau immediately after the previous ramp and of a previous plateau duration that is about the same as the previous ramp duration, wherein the first pulse comprises a first voltage ramp having a first ramp duration longer than the previous ramp duration, wherein the first pulse further comprises a first plateau that is immediately after the first voltage ramp and that has a first plateau duration that is longer than a previous plateau duration of the previous pulse and that is about the same as the first ramp duration.
4 more elements
Dependencies are inferred from the claim text.