Semiconductor memory device
AssigneeSK hynix Inc.
InventorsJae-Seung Lee, No-Geun Joo
Life of this patent
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Abstract
A semiconductor memory device includes a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal; a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal; a second count circuit suitable for counting the second clock signal and generating a second count code signal; and a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.
Claims28
A semiconductor memory device comprising:
- a first count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a first count code signal, based on a burst refresh command signal;
- a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal;
- a second count circuit suitable for counting the second clock signal and generating a second count code signal;
- and
- a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the first count code signal and the second count code signal.
A semiconductor memory device comprising:
- a count circuit suitable for counting a first clock signal which continuously toggles in each burst refresh cycle, and generating a count code signal, based on a burst refresh command signal;
- a cycle guide circuit suitable for generating a second clock signal which toggles once in each burst refresh cycle, based on the burst refresh command signal and a precharge signal;
- a randomization circuit suitable for generating a random code signal corresponding to a random value in each burst refresh cycle, based on the second clock signal;
- and
- a control circuit suitable for generating a latch control signal for latching a target address in each burst refresh cycle, based on the count code signal and the random code signal.
A semiconductor memory device comprising:
- a memory region suitable for performing a normal operation based on a normal address signal, and performing a target refresh operation based on a target address signal;
- a refresh controller suitable for generating a latch control signal which is activated for a limit period different from a previous limit period included in a previous burst refresh cycle, in each burst refresh cycle, based on a burst refresh command signal;
- and
- an address latch suitable for latching the normal address signal which is inputted for the different limit period, as the target address signal, in each burst refresh cycle, based on the latch control signal.
Dependencies are inferred from the claim text.