Apparatuses and methods for logic/memory devices
AssigneeMicron Technology, Inc.
InventorRichard C. Murphy
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.
Claims21
1-19. (canceled)
An apparatus, comprising:
- a plurality of memory components adjacent to and coupled to one another;
- a logic component coupled to the plurality of memory components;
- wherein at least one memory component comprises a memory device, the memory device comprising:
- an array of memory cells;
- sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component;
- and
- timing circuitry coupled to the array and sensing circuitry, the timing circuitry configured to control timing of operations for the sensing circuitry;
- and
- wherein the logic component comprises control logic coupled to the timing circuitry, the control logic configured to execute instructions to cause the sensing circuitry to perform the operations.
The apparatus of claim 1, wherein:
- the array of memory cells is a dynamic random access memory (DRAM) array;
- the timing circuitry is separate from double data rate (DDR) registers used to control read and write DRAM access requests for the array.
The apparatus of claim 1, wherein the timing circuitry and the control logic are in different clock domains and operate at different clock speeds.
The apparatus of claim 1, wherein the operations include logical AND, OR, and/or XOR Boolean operations.
The apparatus of claim 1, wherein the control logic includes a reduced instructions set computer (RISC) type controller which is configured to operate on processing in memory (PIM) commands.
The apparatus of claim 1, wherein:
- the control logic is coupled to a sequencer on the logic component;
- the control logic is a microcoded engine;
- and
- wherein the control logic and the sequencer can execute microcode instructions and coordinate processing in memory (PIM) operations on the logic component, respectively.
The apparatus of claim 6, wherein the timing circuitry is coupled to the control logic and is configured to control timing of logical operations using the sensing circuitry.
The apparatus of claim 1, wherein the logic component and the plurality of memory components comprise:
- a plurality of stacked dynamic random access memory (DRAM) memory die coupled to a logic die by through silicon vias (TSVs) to form a processing in memory (PIM) device.
A method for operating a memory device:
- receiving a processing in memory (PIM) request at a logic die in a logic die and a memory die stack;
- executing microcode instructions on the logic die to cause a logical operation to be performed on the memory die;
- and
- applying a scheduling policy on the logic die between received memory array requests and received PIM requests.
The method of claim 9, wherein the method comprises applying a priority to memory array requests over PIM requests.
The method of claim 9, wherein the method comprises applying a priority to PIM requests over memory array requests.
The method of claim 9, wherein the method comprises:
- using timing circuitry on the memory die to control timing of logical operations using sensing circuitry on pitch with a memory array on the memory die;
- using control logic on the logic die to execute the microcode instructions;
- and
- operating the timing circuitry and the control logic at different clock speeds.
The method of claim 12, wherein the method comprises using timing circuitry on the memory die which is separate from double data rate (DDR) control registers associated with the memory array.
A method for operating a logic/memory device, comprising:
- receiving processing in memory (PIM) requests at a logic die of the logic/memory device;
- receiving memory array requests at the logic die;
- using control logic on the logic die to cause logical operations to be performed on sensing circuitry associated with a memory array on a memory die of the logic/memory device;
- and
- using timing circuitry on the memory die to provide timing for the logical operations on the memory die.
The method of claim 14, wherein the method comprises:
- using a state machine on the memory die as the timing circuitry to provide timing for the logical operations;
- and
- using double data rate (DDR) control registers, separate from the timing circuitry, to provide access to the memory array.
The method of claim 14, wherein the method comprises using a reduced instructions set computer (RISC) type controller on the logic die as the control logic to cause the logical operations to be performed on the sensing circuitry.
The method of claim 14, wherein using the control logic on the logic die comprises using the control logic to:
- fetch microcode instructions from the memory array;
- decode the microcode instructions into function calls implemented by a sequencer on the logic die.
The method of claim 14, wherein the method comprises using a sequencer associated with the timing circuitry on the memory die to generate sequences of operation cycles to perform the logical operations on the sensing circuitry.
The method of claim 14, wherein using the control logic on the logic die comprises using the control logic to execute microcode instructions on the logic die to cause logical operations to be performed on the memory die.
The method of claim 14, wherein the method comprises using arbitration circuitry associated with the control logic on the logic die to apply a scheduling policy between received memory array requests and received PIM requests.
Dependencies are inferred from the claim text.