US 2018/0294026 A1 · SEMICONDUCTOR DEVICE AND SYSTEM

Abstract

A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

Claims18

Dependent claims

A semiconductor device comprising:

a first buffer configured to buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal;
a second buffer configured to generate a second data strobe buffering signal based on the first input signal and a reference voltage;
a divider circuit configured to divide the second data strobe buffering signal to generate a divided signal and a divided bar signal;
and
an internal signal generation circuit configured to generate a first data latch timing signal, a second data latch timing signal, a third data latch timing signal and a fourth data latch timing signal having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided bar signal.

2 more elements

A semiconductor device comprising:

a set circuit configured to generate and output a set signal based on a command and an address;
a fuse circuit configured to generate and output a fuse signal having a level determined in accordance with a cutting of a fuse;
a data latch timing signal generation circuit configured to generate a plurality of data latch timing signals based on the set signal, the fuse signal, a data strobe signal and a data strobe bar signal or based on the data strobe signal, the data strobe bar signal and a reference voltage;
and
a data sort circuit configured to latch and sort data based on the data latch timing signals to generate and output internal data.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor device and system

Life of this patent

Semiconductor device and system

Life of this patent

Abstract

Claims18