Memory macro and method of operating the same

A memory macro comprising:

• a first set of memory cells arranged in columns and rows, the columns of memory cells being arranged in a first direction, the rows of memory cells being arranged in a second direction different from the first direction, each memory cell of the first set of memory cells being configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage, the first voltage being different from the second voltage;
• a second set of memory cells including a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode, the set of retention circuits being responsive to a set of control signals, and being arranged in a first column, the first column being arranged in the first direction and being located along a first edge of the memory macro;
• a set of dummy memory cells arranged in a first row in the second direction, and being located along a second edge of the memory macro;
• a first set of conductive lines overlapping the first set of memory cells, and being coupled to the set of retention circuits and each memory cell of the first set of memory cells, the first set of conductive lines extending in the second direction;
• and
• a second set of conductive lines overlapping the second set of memory cells, being coupled to the set of retention circuits, and extending in the first direction.

A method of operating a memory macro, the method comprising:

• changing an operational mode of a first set of memory cells of the memory macro from a first mode to a second mode in response to a first signal, the first signal indicating the operational mode of the first set of memory cells, the changing the operational mode comprises:
• turning on or off a retention circuit based on the first signal, the retention circuit being part of a second set of memory cells;
• and
• adjusting a voltage provided to the first set of memory cells,
• wherein the retention circuit is coupled to the first set of memory cells by at least a first conductive line or a second conductive line, and at least one of the following configurations:
• (a) the first set of memory cells, the second set of memory cells and the retention circuit are arranged in a column of the memory macro;
• or
• (b) the first set of memory cells, the second set of memory cells and the retention circuit are arranged in a row of the memory macro.