Low swing bitline for sensing arrays

Read merge circuitry, comprising:

• clipper circuitry coupled to a local bitline (LBL) node and to be coupled to a read port node of a bitcell array, the clipper circuitry to provide a voltage drop between the read port node and the LBL node;
• precharge circuitry coupled to the LBL node and a power supply that provides an input voltage, the precharge circuitry to precharge the LBL node to the input voltage based on a precharge signal;
• keeper circuitry coupled to the LBL node and the power supply, the keeper circuitry to maintain a value of the LBL node;
• a first NAND gate coupled to the keeper circuitry and the LBL node, the first NAND gate to control the keeper circuitry based on a value of the LBL node;
• and
• a second NAND gate coupled to the LBL node and to be coupled to a global bitline (GBL) node for a set dominant latch, the second NAND gate to drive a value of the GBL node based, at least partially, on the value of the LBL node.

A system comprising:

• a printed circuit board (PCB);
• a memory device mounted to the PCB, the memory device comprising:
• bitcell arrays;
• clipper circuitry coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node;
• read merge circuitry coupled to the clipper circuitry, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node;
• and
• a set dominant latch coupled to the GBL node to sense the value of the GBL node.