Memory devices comprising a write assist circuit

A memory device comprising:

• a write driver;
• and
• a write assist circuit,
• wherein the write assist circuit includes:
• a first PMOS transistor connected between a cell voltage and an output node of the write assist circuit:
• a second PMOS transistor having a gate connected with a ground voltage and a first end connected with the output node;
• a first NMOS transistor connected with a second end of the second PMOS transistor and turned on or turned off according to a first signal from the write driver;
• and
• a second NMOS transistor connected in parallel with the first NMOS transistor and turned on or turned off according to a second signal provided from the write driver,
• wherein the first and second PMOS transistors are on a PMOS area of a substrate along a first direction perpendicular to a gate formation direction,
• wherein the first and second NMOS transistors are on an NMOS area of the substrate along the first direction, and
• wherein the second end of the second PMOS transistor is connected with the first NMOS transistor through a contact area along the gate formation direction.

A memory device comprising:

• a memory cell;
• a write assist circuit configured to deliver a cell voltage or an assist voltage to the memory cell, wherein the assist voltage is smaller than the cell voltage;
• and
• a write driver connected to the memory cell by a bit line pair, the write driver configured to receive a column selection signal to select whether to provide write data to the memory cell and, responsive to the column selection signal, generate an assist selection signal to the write assist circuit,
• wherein, if the memory cell is selected to receive write data by the column selection signal, the write assist circuit is configured to deliver the assist voltage to the memory cell, and, if the memory cell is not selected to receive write data by the column selection signal, the write assist circuit is configured to deliver the cell voltage to the memory cell.