US 2018/0294017 A1 · SENSE AMPLIFIER WITH NON-IDEALITY CANCELLATION

Abstract

A sense circuit includes memory cell characterization circuitry, storage circuitry, switching circuitry, and bit line biasing circuitry. The sense circuit is configured to perform a sense operation to sense a characterization of a memory cell. During a pre-charge phase, the memory cell characterization circuitry and the bit line biasing circuitry set differential voltages in the storage circuitry to levels dependent on input offset voltages according to certain polarities. The storage circuitry maintains the differential voltages during the sense phase, allowing the memory cell characterization circuitry to cancel output the input offset voltages when generating output voltages used to identify a characterization of the memory cell. The memory cell characterization circuitry also generates its output voltage based on a reference current through a reference bit line. Doing so may allow the memory cell characterization circuitry to cancel out background noise current generated on the bit line during the sense operation.

Claims20

Dependent claims

A circuit comprising:

a memory cell;
a bit line coupled to the memory cell;
an amplifier configured to:
during a first time period:
set a first voltage to a predetermined voltage level adjusted by an input offset voltage of the amplifier according to a first polarity;
and
set a second voltage to the predetermined voltage level;
and
during a second time period:
generate a first comparison voltage in response to a first sum input voltage dependent on the predetermined voltage level adjusted by the input offset voltage according to the first polarity and the input offset voltage according to a second polarity opposite the first polarity;
and
generate a second comparison voltage in response to a second sum input voltage;
and
a comparator configured to:
upon completion of the second period, compare a voltage level of the first comparison voltage and a voltage level of the second comparison voltage;
and
output an output signal indicative of a characterization of the memory cell in response to the comparison.

14 more elements

A circuit comprising:

an amplifier;
storage circuitry configured to:
during a sense phase of a sense operation:
maintain a first differential voltage based on a first voltage;
and
maintain a second differential voltage based on a second voltage;
switching circuitry configured to:
during a pre-charge phase of the sense operation:
connect a first output terminal of the amplifier to a first node of a first input terminal of the amplifier to generate the first voltage;
and
connect a second output terminal of the amplifier to a second node of a second input terminal of the amplifier to generate the second voltage;
and
during the sense phase:
disconnect the first output terminal from the first node and the second output terminal from the second node,
wherein the amplifier, in response to the disconnection, is configured to generate a first comparison voltage based on the first differential voltage and a second comparison voltage based on the second differential voltage;
and
a comparator configured to indicate a behavior of a memory cell in response to being biased during the sense operation based on the first comparison voltage and the second comparison voltage upon completion of the sense phase.

14 more elements

A system comprising:

a memory cell;
a bit line connected to the memory cell;
a reference bit line;
a first amplifier configured to:
bias the bit line with a bit line bias voltage;
during a pre-charge phase of a sense operation, set a first differential voltage of a first charge-charge storing circuit to depend on a first input offset voltage of the first amplifier;
and
during a sense phase of the sense operation, generate a first output voltage dependent on a first sense voltage amount and the first input offset voltage, wherein the first sense voltage amount is indicative of a first current drawn through the bit line;
a second amplifier configured to:
bias the bit line with a bit line bias voltage;
during a pre-charge phase of the sense operation, set a second differential voltage of a second charge-storing circuit to depend on a second input offset voltage of the second amplifier;
and
during a sense phase of the sense operation, generate a second output voltage dependent on a second sense voltage amount and the second input offset voltage, wherein the second sense voltage amount is indicative of a second current drawn through the bit line;
a third amplifier configured to, during the sense phase:
generate a first comparison voltage dependent on the first differential voltage and the first output voltage;
and
generate a second comparison voltage dependent on the second differential voltage and the second output voltage;
and
a comparator configured to:
compare the first comparison voltage and the second comparison voltage;
and
in response to the comparison, generate an output signal indicative of a behavior of the memory cell in response to being biased during the sense operation.

19 more elements

Dependencies are inferred from the claim text.

Sense amplifier with non-ideality cancellation

Life of this patent

Sense amplifier with non-ideality cancellation

Life of this patent

Abstract

Claims20