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US 2018/0293780 A1Published application
Dual path sequential element to reduce toggles in data path
AssigneeIntel Corporation
InventorsSubramaniam Maiyuran, Sanjeev S. Jahagirdar, Kiran C. Veernapu, Eric J. Asperheim, Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu
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Abstract
Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
Claims24
An apparatus comprising:
- switching logic, at least a portion of which is in hardware, to cause signals for a single data path of a processor to be directed to at least two separate data paths,
- wherein at least one of the two separate data paths is to be power gated to reduce signal toggles in the at least one data path.
An apparatus comprising:
- logic, at least a portion of which is in hardware, to cause signals for a single data path of a processor to be directed to at least two separate data paths,
- wherein the at least two separate data paths are to omit one or more middle stage flops.
An apparatus comprising:
- logic, at least a portion of which is in hardware, to cause one or more of a plurality of flops in a data path of a processor to be bypassed in response to a determination that the processor is to run at a first frequency instead of a second frequency,
- wherein the first frequency is lower than the second frequency.
Dependencies are inferred from the claim text.