Apparatus and method for managing data bias in a graphics processing architecture

A method comprising:

• executing instructions and processing data on a processor comprising on one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels;
• executing graphics instructions and processing graphics data on a graphics processing unit (GPU), wherein the GPU and processor cores are to share a virtual address space for accessing a system memory;
• the GPU to address a GPU memory through the virtual address space shared by the processor cores and GPU;
• and
• storing an indication, for each of a plurality of blocks of data, whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, then:
• accessing the data by the GPU from the GPU memory without necessarily accessing the processor's cache coherence controllers, and
• processing requests for the data from the processor cores as uncached requests, preventing the data from being cached in the one or more cache levels of the processor.

A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

• executing instructions and processing data on a processor comprising on one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels;
• executing graphics instructions and processing graphics data on a graphics processing unit (GPU), wherein the GPU and processor cores are to share a virtual address space for accessing a system memory;
• the GPU to address a GPU memory through the virtual address space shared by the processor cores and GPU;
• and
• storing an indication, for each of a plurality of blocks of data, whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, then:
• accessing the data by the GPU from the GPU memory without necessarily accessing the processor's cache coherence controllers, and
• processing requests for the data from the processor cores as uncached requests, preventing the data from being cached in the one or more cache levels of the processor.