Memory module and memory system including the same
AssigneeSK hynix Inc.
InventorJong-Ho JUNG
Life of this patent
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Abstract
A memory module includes: a plurality of memory devices; a plurality of data buffers suitable for receiving a write data transferred from a memory controller, and transferring a read data to the memory controller; and a module controller suitable for: controlling the plurality of the memory devices and the plurality of the data buffers under a control of the memory controller; and, during a read operation, transferring one or more control signals to the plurality of the data buffers through a buffer communication bus after delaying the control signals by a difference between a first column address strobe (CAS) latency value, which is a set value of the memory module, and a second CAS latency value, which is a set value of the plurality of the data buffers.
Claims16
A memory module, comprising:
- a plurality of memory devices;
- a plurality of data buffers suitable for receiving a write data transferred from a memory controller, and transferring a read data to the memory controller;
- and
- a module controller suitable for:
- controlling the plurality of the memory devices and the plurality of the data buffers under a control of the memory controller;
- and,
- during a read operation, transferring one or more control signals to the plurality of the data buffers through a buffer communication bus after delaying the control signals by a difference between a first column address strobe (CAS) latency value, which is a set value of the memory module, and a second CAS latency value, which is a set value of the plurality of the data buffers.
A memory system, comprising:
- a memory module;
- and
- a memory controller suitable for transferring a command, an address, and a write data to the memory module, and receiving a read data from the memory module,
- wherein the memory module comprises:
- a plurality of memory devices;
- a plurality of data buffers suitable for receiving the write data from the memory controller, and transferring the read data to the memory controller;
- and
- a module controller suitable for:
- controlling the plurality of the memory devices and the plurality of the data buffers under a control of the memory controller, and,
- during a read operation, transferring one or more control signals to the plurality of the data buffers through a buffer communication bus after delaying the control signals by a difference between a first column address strobe (CAS) latency value, which is a set value of the memory module, and a second CAS latency value, which is a set value of the plurality of the data buffers.
Dependencies are inferred from the claim text.