# US 2018/0254780 A1 · Resistive interpolation for an amplifier array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0254780 A1 - Document ID: US20180254780A1 - Status: Published application - Kind: A1 - Application number: 15/911,141 - Filed: 2018-03-04 - Published: 2018-09-06 - Earliest claimed: 2017-03-03 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Robert Callaghan Taft; Alexander Bodem - Web page: https://patentgrep.com/patent/US20180254780A1 ## CPC - H03M 1/203: {using an analogue interpolation circuit} - H03M 1/205: {using resistor strings for redistribution of the original reference signals or signals derived therefrom} - H03F 3/19: with semiconductor devices only - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03M 1/1245: {Details of sampling arrangements or methods} - H03M 1/445: {the stages being of the folding type} - H03F 2200/451: the amplifier being a radio frequency amplifier - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03F: AMPLIFIERS ## Abstract A circuit including an amplifier array including an amplifier stage with M amplifiers (M≥2), connected to a resistor interpolator (interpolation order N≥2) including an input row and at least a second row, each row comprising interpolation resistors connected in series at nodes. The input row including M driven nodes connected to a respective amplifier, and connected in parallel to the second row, with at least some first-row interpolation nodes connected to corresponding second-row interpolation nodes. The resistor interpolator comprising at least one multi-row interpolation cell, with: in the input row, a driven node coupled through first and second interpolation resistors to respective adjacent first and second interpolation nodes; and in the second row, third and fourth interpolation nodes coupled through third and fourth interpolation resistors to an intermediate fifth interpolation node; and with the first and second interpolation nodes connected respectively to the third and fourth interpolation nodes. ## Claims ### Claim 1 A circuit including a resistive interpolator, comprising: an input terminal to receive an input value; an amplifier array, including an amplifier stage with M amplifiers (M≥2), each coupled to the input terminal to receive the input value; a resistor interpolator configured to provide an interpolation order N (N≥2), and including an input row and at least a second row, each row comprising multiple interpolation resistors connected in series at nodes, the input row including M driven nodes connected to a respective amplifier, and (N−1) interpolation nodes intermediate each of adjacent driven nodes, and the input row connected in parallel to the second row, with at least some of the interpolation nodes of the first row connected to corresponding interpolation nodes of the second row; the resistor interpolator including at least one multi-row interpolation cell, comprising: in the input row, a driven node connected to first and second interpolation resistors connected between the driven node and respective adjacent first and second interpolation nodes; in the second row, third and fourth interpolation resistors connected between respective third and fourth interpolation nodes and an intermediate fifth interpolation node; the first and second interpolation nodes of the input row connected respectively to the third and fourth interpolation nodes of the second row. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the input row includes M interpolation cells, each including a respective one of the M driven nodes, so that the second row includes zero driven nodes. ### Claim 3 (depends on 1) The circuit of claim 1, wherein the input row and the second row are configured for open loop interpolation, with the input row and the second row each including [(M−1)×N] interpolation resistors connected in series at [((M−1)×N)+1] nodes. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the input row and the second row are configured for closed loop interpolation, with the input row and the second row each including (M×N) interpolation resistors connected in series at (M×N) nodes. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the interpolation resistors do not all have the same resistance value. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the input value is a differential input value, the interpolation resistors are differential interpolation resistors, and the amplifier stage is a differential amplifier stage with M differential amplifiers or 2×M single-ended amplifiers. ### Claim 7 (depends on 1) The circuit of claim 1, further comprising multiple cascaded interpolation stages: each interpolation stage comprising the amplifier array and the resistor interpolator; each interpolation stage except the last interpolation stage having its output nodes coupled as inputs to respective amplifiers of a next interpolation stage. ### Claim 8 (depends on 1) The circuit of claim 1, wherein the number of amplifiers M is greater than the number of driven nodes, and at least some of the amplifier outputs are connected to respective driven nodes with a folding factor to couple multiple amplifiers to the driven node. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the circuit is an analog-to-digital converter (ADC). ### Claim 10 (depends on 9) The circuit of claim 9, wherein the ADC includes at least one amplifier array is a folded amplifier array in which the number of amplifiers M is greater than the number of driven nodes, and at least some of the amplifier outputs are connected to respective driven nodes with a folding factor to couple multiple amplifiers the driven node. ### Claim 11 (depends on 10) The circuit of claim 10, wherein: the amplifier array is configured with folding factor of three; and the resistor interpolator is configured with an interpolation order of three. ### Claim 12 A circuit for analog-to-digital conversion, comprising: an input terminal to receive an input value; at least one folding interpolated amplifier array, including a folding amplifier stage with M amplifiers (M≥4), each coupled to the input terminal to receive the input value, the M amplifiers configured with a folding factor of N (N≥2) to provide M/N amplifier stage outputs; a resistor interpolator coupled to receive the M/N amplifier stage outputs, and configured to provide an interpolation order N (N≥2), and including an input row and at least a second row, each row comprising multiple interpolation resistors connected in series at nodes, the input row including M/N driven nodes connected to a respective amplifier, and (N−1) interpolation nodes intermediate each of adjacent driven nodes, and the input row connected in parallel to the second row, with at least some of the interpolation nodes of the first row connected to corresponding interpolation nodes of the second row; the resistor interpolator including at least one multi-row interpolation cell, comprising: in the input row, a driven node connected to first and second interpolation resistors connected between the driven node and respective adjacent first and second interpolation nodes; in the second row, third and fourth interpolation resistors connected between respective third and fourth interpolation nodes and an intermediate fifth interpolation node; the first and second interpolation nodes of the input row connected respectively to the third and fourth interpolation nodes of the second row. ### Claim 13 (depends on 12) The circuit of claim 12, wherein the input row includes M/N interpolation cells, each including a respective one of the M driven nodes, so that the second row includes zero driven nodes. ### Claim 14 (depends on 12) The circuit of claim 12, wherein the input row and the second row are configured for one of open loop interpolation, with the input row and the second row each including [(M/N−1)×N] interpolation resistors connected in series at [((M/N−1)×N)+1] nodes. ### Claim 15 (depends on 12) The circuit of claim 12, wherein the input row and the second row are configured for closed loop interpolation, with the input row and the second row each including (M) interpolation resistors connected in series at (M) nodes. ### Claim 16 (depends on 12) The circuit of claim 12, wherein the interpolation resistors do not all have the same resistance value. ### Claim 17 (depends on 12) The circuit of claim 12, wherein the input value is a differential input value, the interpolation resistors are differential interpolation resistors, and the amplifier stage is a differential amplifier stage with M differential amplifiers or 2×M single-ended amplifiers. ### Claim 18 (depends on 12) The circuit of claim 12, further comprising multiple cascaded amplifier array stages: each amplifier array stage comprising the amplifier array and the resistor interpolator; each amplifier array stage except the last interpolation stage having its output nodes coupled as inputs to respective amplifiers of a next amplifier array stage. ### Claim 19 (depends on 12) The circuit of claim 12, wherein: the amplifier stage is configured with folding factor of three; and the resistor interpolator is configured with an interpolation order of three.