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US 2018/0231949 A1Published application
Safety Controller Using Hardware Memory Protection
AssigneeRockwell Automation Technologies, Inc.
InventorsJoseph P. Izzo, Nicholas L. Stay
Life of this patent
Estimating the term…
Abstract
Hardware memory management units are used in an integrated safety/non-safety industrial computer to allow shared memory architecture processors to implement safety and non-safety reduced risk of memory corruption. Testing of the memory management unit of the non-safety processor may provide a periodic writing to protected memory to invoke a protection fault providing a report to the safety processor.
Claims20
A safety industrial controller comprising:
- a first and second processor each including hardware memory management units;
- an electronic memory having a plurality of addresses electronically addressable by both the first and second processor and holding a first and second program executable by the first and second processors respectively;
- and
- I/O circuitry adapted to communicate between industrial actuators and sensors and the safety industrial controller including at least one of the first and second processors;
- wherein the hardware memory management units each include a memory protection table having entries mapping to addresses of the electronic memory and wherein the entries hold protection flags which when set block a writing to addresses of the entries;
- wherein the first processor executes the first program to:
- (i) set protection flags of its memory management unit to permit writing to the electronic memory in a first region holding the first program and not in a second region holding the second program;
- and
- (ii) periodically attempt to write to the second region;
- and
- wherein the second processor executes the second program to:
- (i) set protection flags of its memory management unit to permit writing to the electronic memory in the second region holding the second program and not in the first region holding the first program;
- and
- (ii) confirm that the first processor is blocked by its memory management unit from writing in the second region.
11 more elements
A method of providing integrated safety and non-safety control using a safety industrial controller having:
- a first and second processor each including hardware memory management units;
- an electronic memory having a plurality of addresses electronically addressable by both the first and second processor and holding a first and second program executable by the first and second processors respectively;
- and
- I/O circuitry adapted to communicate between industrial actuators, and sensors and the safety industrial controller including at least one of the first and second processors;
- wherein the hardware memory management units each include a memory protection table having entries mapping to addresses of the electronic memory and wherein the entries hold protection flags which once set up block a writing to addresses of the entries;
- the method including the steps of:
- operating the first processor to:
- (i) set protection flags of its memory management unit to permit writing to the electronic memory in a first region holding the first program and not in a second region holding second program;
- and
- (ii) to periodically attempt to write to the second region;
- and
- operating the second processor to:
- (i) set protection flags of its memory management unit to permit writing to the electronic memory in the second region holding the second program and not in the first region holding the first program;
- and
- (ii) confirm that the first processor is blocked by its memory management unit from writing in the second region.
12 more elements
A computer architecture for a safety industrial controller:
- a first and second processor each including hardware memory management units;
- an electronic memory having a plurality of addresses electronically addressable by both the first and second processor and holding a first and second program executable by the first and second processors respectively;
- wherein the hardware memory management units each include a memory protection table having entries mapping to addresses of the electronic memory and wherein the entries hold protection flags which when set block a writing to addresses of the entries;
- wherein the first processor is configured to:
- (i) set protection flags of its memory management unit to permit writing to the electronic memory in a first region holding the first program and not in a second region holding the second program;
- and
- (ii) periodically attempt to write to the second region;
- and
- wherein the second processor is configured to:
- (i) set protection flags of its memory management unit to permit writing to the electronic memory in the second region holding the second program and not in the first region holding the first program;
- and
- (ii) confirm that the first processor is blocked by its memory management unit from writing in the second region.
9 more elements
Dependencies are inferred from the claim text.