List decode circuits
AssigneeHewlett Packard Enterprise Development LP
InventorsChris Michael Brueggen, Ron M. Roth
Life of this patent
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AssigneeHewlett Packard Enterprise Development LP
InventorsChris Michael Brueggen, Ron M. Roth
Estimating the term…
Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.
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Dependencies are inferred from the claim text.