Cascaded counter circuit with pipelined reload of variable ratio determined values

A computing system, comprising:

• a plurality of processing cores;
• a memory controller, said memory controller coupled to a system memory;
• a display;
• a counter circuit comprising ordered state element circuits where a respective clock input of a state element circuit is fed by a data output of a preceding lower ordered bit state element, said counter circuit also being programmable to enable different amounts to be counted by said counter circuit, wherein respective reload values for said amounts are received at said state elements as a respective asynchronous set or reset, said counter having an input that receives an input clock and an output that provides an output clock having a divided down frequency of said input clock.