Nonvolatile memory with erase gate region

A nonvolatile memory (NVM) cell, comprising:

• a semiconductor substrate of a first conductivity type;
• a first oxide define (OD) region in the semiconductor substrate;
• a second oxide define (OD) region being spaced apart from the first OD region;
• an erase gate (EG) region disposed in the second OD region;
• a trench isolation region separating the first OD region from the second OD region;
• a select transistor disposed on the first OD region;
• a floating gate transistor serially connected to the select transistor and being disposed on the first OD region, wherein the floating gate transistor comprises a floating gate overlying the first OD region;
• and
• a first floating gate extension continuously extending from the floating gate to the second OD region, wherein the first floating gate extension comprises a P+ doped segment and an N+ doped segment with a P+/N+ interface therebetween, wherein the P+/N+ interface is situated closer to the first OD region.