Method for fabricating auto-aligned interconnection elements for a 3d integrated circuit

Method for fabricating transistors for an integrated circuit equipped with several superimposed levels of transistors, comprising the following steps:

• a) forming, on a given level equipped with one or more transistors made at least partially in a first semiconductor layer:
• a stack comprising at least one first region of a second semiconductor layer suitable for receiving an N-type transistor channel and at least one second region of the second semiconductor zone suitable for receiving a P-type transistor channel of a level above the given level, where the stack moreover comprises a continuous layer made of conductive or doped semiconductor material and called the ground plane, as well as an insulating layer between the ground plane and the second semiconductor layer, then
• b) carrying out at least one thermal annealing for activation of source and drain region of said N type transistor and of said P type transistor by exposure to a laser, said source and drain regions being in the form of one or more doped zones of the second semiconductor layer and/or doped semiconductor blocks formed on the second semiconductor layer, where the source and drain regions exposed to the laser are located on the side of an upper face of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect from the laser a part of the circuit located on the side of a lower face of the ground plane continuous layer, then
• c) cutting up of the ground plane continuous layer into at least one first portion and at least one second portion separated from the first portion, where the first portion is configured to allow biasing of the first region, where the second portion is configured to allow biasing of the second region.