Computer implemented method for determining intrinsic parameter in a stacked nanowires mosfet

A computer implemented method for determining at least one intrinsic parameter of a stacked nanowires/nanosheets gate-all-around (GAA) metal oxide semiconductor field effect transistor (MOSFET) comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps:

• measuring by at least one imaging method the following geometrical parameters of the MOSFET:
• the number of stacked nanowires/nanosheets Nw,
• the width Ww,i, of the nanowire/nanosheet number i, i being an integer from 1 to Nw,
• the thickness of the nanowire/nanosheet Hw,i, number i, i being an integer from 1 to Nw,
• the corner radius Rw,i of the nanowire/nanosheet number i, i being an integer from 1 to Nw, Rw,i;
• calculating, using a physical processor and the measured geometrical parameters, a surface potential x normalized by a thermal voltage ϕT given by ϕT=kBT/q;
• measuring electrically the total gate capacitance for a plurality of gate voltages;
• determining, using the measured total gate capacitance and the calculated normalized surface potential, the at least one intrinsic parameter of the stacked nanowires/nanosheets MOSFET.