US 2018/0129475 A1 · BIT-SERIAL MULTIPLIER FOR FPGA APPLICATIONS

Abstract

A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths (e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/O) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor.

Claims20

Dependent claims

A system, comprising:

a general-purpose processor circuit;
and
a field-programmable gate array (FPGA) circuit coupled to the general-purpose processor circuit to serially receive a binary multiplicand and a binary multiplier and to provide a result of a bit-serial multiplication performed on the binary multiplicand and the binary multiplier;
wherein the FPGA circuit is configured to perform the bit-serial multiplication using a bit-serial multiplication circuit, the performing the bit-serial multiplication including:
serially receiving the binary multiplicand;
serially receiving the binary multiplier;
and
contemporaneously during the serially receiving, providing two bits comprising the least significant bit and the second least significant bit of the result of the multiplication.

5 more elements

Dependencies are inferred from the claim text.

Bit-serial multiplier for fpga applications

Life of this patent

Bit-serial multiplier for fpga applications

Life of this patent

Abstract

Claims20