Rf interconnect
AssigneeInnovative Micro Technology
InventorChristopher S. GUDEMAN
Life of this patent
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Abstract
We describe below a structure and process that uses through-silicon-vias and wafer-to-wafer bonding to create transmission lines. The method may require one electroplating step, 3 etch steps, 4 lithography steps, one grind and polish step, and one wafer bonding step, totaling ten process steps per transmission line layer.
Claims20
A method for forming a transmission line, comprising:
- forming at least one signal via and one ground via though a first substrate;
- forming a shield layer over the substrate which is configured to block RF radiation;
- and coupling the ground via to the shield layer.
The method of claim 5, wherein the shield layer comprises a metal layer that covers a majority of an inner surface of the device cavity.
An interconnect for an RF signal handling device, comprising:
- at least one signal via and one ground via formed though a first substrate;
- a shield layer formed over the first substrate wherein the shield layer is configured to block RF radiation, where in the
- the ground via is electrically coupled to the shield layer.
The interconnect for an RF signal handling device of claim 10, further comprising:
- a thermal oxide which covers the surfaces of the substrate and walls of the ground via and signal via, and wherein the shield layer is between about 0.5 and 5 microns thick.
An interconnect structure using a plurality of semiconductor substrates, comprising;
- a first and a second substrate, each having one side coated with a highly conductive, unpatterned metal to form a shielding layer,
- an obverse side of each of the first and second substrate having a highly conductive metal patterned, to form RF transmission lines;
- a plurality of copper through substrate vias, that couple electrically the metal on the first surface to the metal on the obverse surface, and
- a plurality of solder bumps which couple the first substrate to the second substrate to for an RF transmission line structure.
The interconnect structure of claim 18, further comprising:
- a third substrate fabricated like the first substrate and second substrate, and coupled to the first and second substrates by a plurality of solder bumps.
The interconnect structure of claim 19, further comprising semiconductor devices electrically attached to at least one of the patterned and the unpatterned metal, and wherein the patterned and unpatterned metals are configured as co-planar waveguides that transmit signals to or from the semiconductor device,
The printed circuit structure of claim 19, further comprising passive devices electrically coupled to at least one of the patterned and unpatterned metals.
A structure for routing RF signals in 3 dimensions, comprising:
- a ground and a signal through wafer via formed in a first semiconductor wafer;
- a ground and a signal trace that connect the ground and a signal through wafer via on one or both surfaces of the first semiconductor wafer;
- a ground and signal via in a second semiconductor wafer;
- a ground and a signal trace that connects the vias on one or both surfaces of the second wafer;
- wherein ground traces and the signal traces on the second wafer are electrically coupled to the ground traces and the signal traces on the second wafer interconnections between the first and second wafers, when the first wafer is bonded to the second wafer.
Dependencies are inferred from the claim text.