Two-terminal integrated circuits with time-varying voltage-current characteristics including phased-locked power supplies

A two-terminal IC chip, the chip comprising:

• a first chip terminal;
• a second chip terminal;
• a first switch configured to receive a control signal;
• a first capacitor coupled to the first switch;
• a second switch configured to receive the control signal;
• a second capacitor coupled to the second switch;
• a third switch configured to receive the control signal;
• a third capacitor coupled to the third switch;
• wherein:
• a first terminal voltage is a voltage of the first chip terminal;
• a second terminal voltage is a voltage of the second chip terminal;
• and
• a chip voltage is equal to a difference between the first terminal voltage and the second terminal voltage;
• wherein the chip is configured to allow a chip current to flow into the chip at the first chip terminal and out of the chip at the second chip terminal, or to flow into the chip at the second chip terminal and out of the chip at the first chip terminal, the chip current being larger than or equal to zero in magnitude;
• wherein the first switch is further configured to be:
• closed during a first time duration in response to the control signal;
• and
• open during a second time duration in response to the control signal;
• wherein the first capacitor is configured to:
• in response to the first switch being closed, receive a first supply voltage through the first switch during the first time duration;
• in response to the first switch being open, not store any additional power and not allow first stored power to leak out through the first switch during the second time duration;
• and
• output a first output voltage during the first time duration and the second time duration;
• wherein the second switch is further configured to be:
• closed during the first time duration in response to the control signal;
• and
• open during the second time duration in response to the control signal;
• wherein the second capacitor is configured to:
• in response to the second switch being closed, receive the first supply voltage through the second switch during the first time duration;
• in response to the second switch being open, not store any additional power and not allow second stored power to leak out through the second switch during the second time duration;
• and
• output a second output voltage during the first time duration and the second time duration;
• wherein the third switch is further configured to be:
• closed during the first time duration in response to the control signal;
• and
• open during the second time duration in response to the control signal;
• wherein the third capacitor is configured to:
• in response to the third switch being closed, receive a second supply voltage through the third switch during the first time duration;
• in response to the third switch being open, not store any additional power and not allow second stored power to leak out through the third switch during the second time duration;
• and
• output a third output voltage during the first time duration and the second time duration;
• wherein:
• the chip is an integrated circuit;
• and
• the chip does not include any additional chip terminal other than the first chip terminal and the second chip terminal.