Rsa decryption processor and method for controlling rsa decryption processor

A method for controlling an RSA decryption processor, wherein the RSA decryption processor comprises a memory and a parallel processor, the memory is configured to store decryption parameters comprising a private key, and the method comprises:

• receiving a ciphertext set;
• and
• sending a decryption signal comprising the ciphertext set to the parallel processor, so that the parallel processor reads a decryption parameter from the memory in response to receiving the decryption signal, and uses at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts.

A non-transitory storage medium storing one or more programs, the one or more programs when executed by an apparatus, causing the apparatus to perform operations for controlling an RSA decryption processor, wherein the RSA decryption processor comprises a memory and a parallel processor, the memory is configured to store decryption parameters comprising a private key, and the operations comprises:

• receiving a ciphertext set;
• and
• sending a decryption signal comprising the ciphertext set to the parallel processor, so that the parallel processor reads a decryption parameter from the memory in response to receiving the decryption signal, and uses at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts.