Clock recovery circuit, semiconductor integrated circuit device and radio frequency tag
AssigneeFujitsu Limited
InventorKouichi Kanda
Life of this patent
Estimating the term…
Abstract
A clock recovery circuit includes: a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases; a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node; and a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, wherein the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.
Claims16
A clock recovery circuit comprising:
- a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases;
- a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node;
- and
- a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range,
- wherein
- the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.
A semiconductor integrated circuit device comprising:
- a sensor main body circuit coupled to a battery;
- and
- a short-distance radio communication circuit including:
- a phase-locked loop circuit that receives a clock and generates multi-phase clocks having different phases;
- and
- a clock recovery circuit that receives the multi-phase clocks and generates an output clock,
- wherein the clock recovery circuit includes:
- a plurality of switch elements that control coupling between each of the multi-phase clocks and an output node;
- and
- a switch control circuit that compares phases of the multi-phase clocks and input data and controls, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, and
- the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.
A radio frequency tag comprising:
- a semiconductor integrated circuit device including:
- a sensor main body circuit coupled to a battery;
- and
- a short-distance radio communication circuit including:
- a phase-locked loop circuit that receives a clock and generates multi-phase clocks having different phases;
- and
- a clock recovery circuit that receives the multi-phase clocks and generates an output clock;
- and
- an antenna configured to exchange a signal with a reader-writer,
- wherein
- the clock recovery circuit includes:
- a plurality of switch elements that control coupling between each of the multi-phase clocks and an output node;, and
- a switch control circuit that compares phases of the multi-phase clocks and input data and controls, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, and
- the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.
Dependencies are inferred from the claim text.