Clock synchronizing

A clock synchronizing apparatus for a clock synchronizing configuration, the apparatus comprising:

• a processor;
• and
• a non-transitory machine-readable storage medium,
• wherein, by invoking and executing machine-executable instructions corresponding to a clock synchronizing control logic stored on the machine-readable storage medium, the processor is caused to:
• select two different modules from N modules as two reference modules respectively, each of the N modules being provided a clock of a preset frequency to be synchronized, every two adjacent modules of the N modules being coupled by a transmission line of the same length, N being an odd number;
• control each of the reference modules to output a synchronizing signal in a way that the synchronizing signal is simultaneously transmitted in a clockwise direction and an anticlockwise direction until modules other than the reference module in the N modules respectively receive the synchronizing signal once;
• determine a clock error between every two modules that have the same transmission distance from the reference module according to a moment of the synchronizing signal reaching each of the other modules;
• select a calibrating module from the N modules;
• and
• implement clock synchronization between each of the N modules and the calibrating module according to the respective clock errors associated with each of the two reference modules.

A non-transitory computer-readable storage medium having instructions stored thereon which, when executed by one or more processors, cause the one or more processors to perform operations for clock synchronization, the operations comprising:

• coupling every two adjacent modules of a plurality of modules by a respective transmission line, the respective transmission lines having a same length, wherein a number of the plurality of modules is an odd number;
• selecting two different modules from the plurality of modules as two reference modules, respectively;
• obtaining, for each of the reference modules, a respective group of clock errors between every two modules in the plurality of modules;
• selecting a calibrating module from the plurality of modules;
• and
• implementing clock synchronization between each of the plurality of modules and the calibrating module according to the obtained respective groups of clock errors for the two reference modules.