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US 2018/0123734 A1Published application
Deeply-pipelined high-throughput ldpc decoder architecture
AssigneeQUALCOMM Incorporated
InventorsVincent LONCKE, Girish VARATKAR, Thomas Joseph RICHARDSON, Yi CAO
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Abstract
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs.
Claims30
A method for performing low-density parity-check (LDPC) decoding, the method comprising:
- receiving log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- updating the LLRs for each of the encoded bits corresponding to columns of a parity check matrix (PCM), the bit LLRs indicating a probability of a value of each of the encoded bits;
- determining, for each of the encoded bits, an a posteriori LLR for a row of the PCM by processing each LLR within the row, wherein for a first set of the encoded bits, determining the a posteriori LLR comprises using a first number of outdated LLRs, and wherein for a second set of the encoded bits, determining the a posteriori LLR comprises using a second number of updated LLRs, wherein the first set of the encoded bits and the second set of the encoded bits comprise all of the encoded bits;
- utilizing the LLRs to decode the encoded bits.
1 more element
An apparatus for performing low-density parity-check (LDPC) decoding, comprising:
- at least one processor configured to:
- receive log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- update the LLRs for each of the encoded bits corresponding to columns of a parity check matrix (PCM), the bit LLRs indicating a probability of a value of each of the encoded bits;
- determine, for each of the encoded bits, an a posteriori LLR for a row of the PCM by processing each LLR within the row, wherein for a first set of the encoded bits, determining the a posteriori LLR comprises using a first number of outdated LLRs, and wherein for a second set of the encoded bits, determining the a posteriori LLR comprises using a second number of updated LLRs, wherein the first set of the encoded bits and the second set of the encoded bits comprise all of the encoded bits;
- and
- utilize the LLRs to decode the encoded bits;
- and
- a memory coupled with the at least one processor.
5 more elements
An apparatus for performing low-density parity-check (LDPC) decoding, comprising:
- means for receiving configured to receive log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- means for updating configured to update the LLRs for each of the encoded bits corresponding to columns of a parity check matrix (PCM), the bit LLRs indicating a probability of a value of each of the encoded bits;
- means for determining configured to determine, for each of the encoded bits, an a posteriori LLR for a row of the PCM by processing each LLR within the row, wherein for a first set of the encoded bits, determining the a posteriori LLR comprises using a first number of outdated LLRs, and wherein for a second set of the encoded bits, determining the a posteriori LLR comprises using a second number of updated LLRs, wherein the first set of the encoded bits and the second set of the encoded bits comprise all of the encoded bits;
- means for utilizing configured to utilize the LLRs to decode the encoded bits.
1 more element
A non-transitory computer-readable medium for performing low-density parity-check (LDPC) decoding, comprising instructions that, when executed by at least one processor, configures the at least one processor to:
- receive log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- update the LLRs for each of the encoded bits corresponding to columns of a parity check matrix (PCM), the bit LLRs indicating a probability of a value of each of the encoded bits;
- determine, for each of the encoded bits, an a posteriori LLR for a row of the PCM by processing each LLR within the row, wherein for a first set of the encoded bits, determining the a posteriori LLR comprises using a first number of outdated LLRs, and wherein for a second set of the encoded bits, determining the a posteriori LLR comprises using a second number of updated LLRs, wherein the first set of the encoded bits and the second set of the encoded bits comprise all of the encoded bits;
- utilize the LLRs to decode the encoded bits.
1 more element
Dependencies are inferred from the claim text.