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US 2018/0123614 A1Published application
Early termination technique for ldpc decoder architecture
AssigneeQUALCOMM Incorporated
InventorsVincent LONCKE, Yi CAO, Girish VARATKAR
Life of this patent
Estimating the term…
Abstract
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.
Claims20
A method for performing low-density parity-check (LDPC) decoding, the method comprising:
- receiving log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- updating the LLRs corresponding to the encoded bits corresponding to columns of a parity check matrix (PCM), the LLRs indicating a probability of a value of each of the encoded bits, wherein each row of the PCM corresponds to a parity check for the encoded bits;
- iteratively decoding the encoded bits using the PCM, wherein for each iteration of decoding, for each row of the PCM, the LLRs are updated based on a processing of the row of the PCM;
- maintaining an overall parity bit;
- setting the overall parity bit to true at a beginning of an iteration of decoding;
- for each processing of the row of the PCM, adding a result of the parity check for the LLRs to the overall parity bit during the iteration of decoding;
- maintaining a sign flip bit;
- setting the sign flip bit to true at the beginning of the iteration of decoding;
- setting the sign flip bit to false when a sign of any LLR changes during the iteration of decoding;
- and
- stopping iteratively decoding the encoded bits when the sign flip bit and the overall parity bit are set to true at an end of the iteration of decoding.
8 more elements
An apparatus for performing low-density parity-check (LDPC) decoding, the apparatus comprising:
- a memory;
- and
- a processor, the memory and processor being configured to:
- receive log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- update the LLRs corresponding to the encoded bits corresponding to columns of a parity check matrix (PCM), the LLRs indicating a probability of a value of each of the encoded bits, wherein each row of the PCM corresponds to a parity check for the encoded bits;
- iteratively decode the encoded bits using the PCM, wherein for each iteration of decoding, for each row of the PCM, the LLRs are updated based on a processing of the row of the PCM;
- maintain an overall parity bit;
- set the overall parity bit to true at a beginning of an iteration of decoding;
- for each processing of the row of the PCM, add a result of the parity check for the LLRs to the overall parity bit during the iteration of decoding;
- maintain a sign flip bit;
- set the sign flip bit to true at the beginning of the iteration of decoding;
- set the sign flip bit to false when a sign of any LLR changes during the iteration of decoding;
- and
- stop iteratively decoding the encoded bits when the sign flip bit and the overall parity bit are set to true at an end of the iteration of decoding.
11 more elements
A computer readable medium having instructions stored thereon for performing a method for performing low-density parity-check (LDPC) decoding, the method comprising:
- receiving log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- updating the LLRs corresponding to the encoded bits corresponding to columns of a parity check matrix (PCM), the LLRs indicating a probability of a value of each of the encoded bits, wherein each row of the PCM corresponds to a parity check for the encoded bits;
- iteratively decoding the encoded bits using the PCM, wherein for each iteration of decoding, for each row of the PCM, the LLRs are updated based on a processing of the row of the PCM;
- maintaining an overall parity bit;
- setting the overall parity bit to true at a beginning of an iteration of decoding;
- for each processing of the row of the PCM, adding a result of the parity check for the LLRs to the overall parity bit during the iteration of decoding;
- maintaining a sign flip bit;
- setting the sign flip bit to true at the beginning of the iteration of decoding;
- setting the sign flip bit to false when a sign of any LLR changes during the iteration of decoding;
- and
- stopping iteratively decoding the encoded bits when the sign flip bit and the overall parity bit are set to true at an end of the iteration of decoding.
8 more elements
An apparatus for performing low-density parity-check (LDPC) decoding, the apparatus comprising:
- means for receiving log-likelihood ratios (LLRs) corresponding to bits encoded using LDPC encoding;
- means for updating the LLRs corresponding to the encoded bits corresponding to columns of a parity check matrix (PCM), the LLRs indicating a probability of a value of each of the encoded bits, wherein each row of the PCM corresponds to a parity check for the encoded bits;
- means for iteratively decoding the encoded bits using the PCM, wherein for each iteration of decoding, for each row of the PCM, the LLRs are updated based on a processing of the row of the PCM;
- means for maintaining an overall parity bit;
- means for setting the overall parity bit to true at a beginning of an iteration of decoding;
- means for, for each processing of the row of the PCM, adding a result of the parity check for the LLRs to the overall parity bit during the iteration of decoding;
- means for maintaining a sign flip bit;
- means for setting the sign flip bit to true at the beginning of the iteration of decoding;
- means for setting the sign flip bit to false when a sign of any LLR changes during the iteration of decoding;
- and
- means for stopping iteratively decoding the encoded bits when the sign flip bit and the overall parity bit are set to true at an end of the iteration of decoding.
8 more elements
Dependencies are inferred from the claim text.