Forward error correction (fec) emulator

A communications method comprising:

• an emulator module passing received data through a pseudo-random bit sequence (PRBS) verifier to determine error bits;
• grouping the data into symbols according to a forward error correction (FEC) code, wherein the FEC code comprises a GF10 Reed Solomon FEC code;
• grouping the symbols into codewords according to the FEC code;
• counting a number of symbols in a codeword having error bits;
• comparing the number of symbols having error bits to an error correction capability value to determine whether the codeword is correctable;
• storing error statistics based upon the comparing;
• generating a correction signal from the error statistics;
• and
• forwarding the correction signal to a correction module also having the received data and the error bits as inputs, the correction module comprising an AND gate and an exclusive OR (XOR) gate;
• and
• the correction module processing the received data according to the correction signal and the error bits to output a corrected data stream to a bit error rate tester, wherein,
• a first delay First-In First-Out (FIFO) of the correction module delays the error bits to produce a delayed error bus,
• a second delay FIFO of the correction module delays the received data to produce delayed received data, and
• in response to a synchronization signal received from the emulator module, a block alignment state machine of the correction module produces a correction bit mask bus that is combined using the AND gate with the delayed error bus, a product of which is then combined using the XOR gate with the delayed received data in order to create the corrected data stream.

A communications method comprising:

• an emulator module passing received data through a pseudo-random bit sequence (PRBS) verifier to determine error bits;
• grouping the data into symbols according to a forward error correction (FEC) code;
• grouping the symbols into codewords according to the FEC code;
• counting a number of symbols in a codeword having error bits;
• comparing the number of symbols having error bits to an error correction capability value to determine whether the codeword is correctable, wherein the error correction capability value comprises half of a difference between a total number of symbols and a number of payload symbols;
• storing error statistics based upon the comparing;
• generating a correction signal from the error statistics;
• and
• forwarding the correction signal to a correction module also having the received data and the error bits as inputs, the correction module comprising an AND gate and an exclusive OR (XOR) gate;
• and
• the correction module processing the received data according to the correction signal and the error bits to output a corrected data stream to a bit error rate tester, wherein,
• a first delay First-In First-Out (FIFO) of the correction module delays the error bits to produce a delayed error bus,
• a second delay FIFO of the correction module delays the received data to produce delayed received data, and
• in response to a synchronization signal received from the emulator module, a block alignment state machine of the correction module produces a correction bit mask bus that is combined using the AND gate with the delayed error bus, a product of which is then combined using the XOR gate with the delayed received data in order to create the corrected data stream.

A communications method comprising:

• an emulator module passing received data through a pseudo-random bit sequence (PRBS) verifier to determine error bits;
• grouping the data into symbols according to a forward error correction (FEC) code;
• grouping the symbols into codewords according to the FEC code;
• counting a number of symbols in a codeword having error bits;
• comparing the number of symbols having error bits to an error correction capability value to determine whether the codeword is correctable;
• storing error statistics based upon the comparing;
• the emulator module generating a correction signal from the error statistics;
• and
• the emulator module forwarding the correction signal to a correction module also having the received data and the error bits as inputs, the correction module comprising an AND gate and an exclusive OR (XOR) gate, the method further comprising the correction module processing the received data according to the correction signal and the error bits to output a corrected data stream to a bit error rate tester, wherein,
• a first delay First-In First-Out (FIFO) of the correction module delays the error bits to produce a delayed error bus,
• a second delay FIFO of the correction module delays the received data to produce delayed received data, and
• in response to a synchronization signal received from the emulator module, a block alignment state machine of the correction module produces a correction bit mask bus that is combined using the AND gate with the delayed error bus, a product of which is then combined using the XOR gate with the delayed received data in order to create the corrected data stream.